Patchwork Flashrom fails on write. P4 motherboard

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Submitter Stefan Tauner
Date 2013-07-25 19:31:01
Message ID <201307251931.r6PJV2dV032584@mail2.student.tuwien.ac.at>
Download mbox | patch
Permalink /patch/3992/
State New
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Comments

Stefan Tauner - 2013-07-25 19:31:01
On Thu, 25 Jul 2013 20:23:32 +0200
san <san@plusnet.pl> wrote:

> Just uploaded lspci -nn here: http://e-san.info/Flashrom-P4/lspci-nn.txt
> How to lower GPIO by hand (before patch)?

Ah I forgot... I need one verbose flag too for the final patch, so that
we see the subsystem IDs too, sorry. So it should have been lspci -nnv.

I have prepared a preliminary patch that should at least verify if the
reverse engineering is correct, see the attachment.

You can also set this somehow with pciset as you know, I am just not
entirely sure about the exact commands.
you would need to get the gpiobase first with
setpci -s 00:1f.0 58.l
(only bits 6-15 are the base address see datasheet)
and then fetch the old value with
setpci -s 0:1f.0 gpiobase+0x0c
and set it with
setpci -s 0:1f.0 gpiobase+0x0c=...

I would rather just try the patch. :)

Sometimes there happen errors while reverse engineering the code so it
is possible that you actually need to raise the pin instead or that the
pin number is off by one. If you are a bit into programming then I am
sure you can figure out how to refine the patch if necessary, but we
can help you too of course.
Stefan Tauner - 2013-07-25 19:54:04
On Thu, 25 Jul 2013 21:31:01 +0200
Stefan Tauner <stefan.tauner@student.tuwien.ac.at> wrote:

> You can also set this somehow with pciset as you know, I am just not
> entirely sure about the exact commands.
> you would need to get the gpiobase first with
> setpci -s 00:1f.0 58.l
> (only bits 6-15 are the base address see datasheet)
> and then fetch the old value with
> setpci -s 0:1f.0 gpiobase+0x0c
> and set it with
> setpci -s 0:1f.0 gpiobase+0x0c=...

Actually this can't work out (thanks to Kyösti for pointing that out).
Because the gpiobase address is in the separated i/o address space of
the cpu. "The control for the general purpose I/O signals is handled
through a separate 64-byte I/O space."
I am not aware of any distributed binaries that work similar to setpci
but in the i/o space, so you would need to program your own... like the
one described here:
http://flashrom.org/Board_Enable
san - 2013-07-26 01:07:09
Yeah, i tried to understand it about three times...

I'll try again, tommorow. Only thing i found is

=== [code] ===
0262420   $   @   A   W   D   F   L   A   S   H   <   e   ?   e 211   e
0262440 337   e 342   e 370   e 024   f   G   f   0   f 340   e 341   e
0262460 023  \0   D   d 243   f  \0  \0  \0  \0 262  \0   2 333 313   f
0262500   ` 271   N 370 350  \r 001  \f 001 350   $ 001 263 023 212 313
0262520 200 341  \a 267 001 322 347 366 327 212 313 300 351 003 200 301
0262540 214 350   e  \0   " 307 350   k  \0 263 023 212 313 200 341  \a
0262560 267 001 322 347 366 327 212 313 300 351 003 200 301 214 350   H
0262600  \0   " 307 350   N  \0   f   a 313   f   ` 271   N 370 350 303
0262620  \0   $ 376 350 332  \0 263 023 212 313 200 341  \a 267 001 322
0262640 347 212 313 300 351 003 200 301 214 350 035  \0  \n 307 350   #
0262660  \0   f   a 313   f   Q   f   P 271   A 370 350 226  \0 017 266
0262700 320 301 342  \b   f   X   f   Y 303   R 350 347 377 212 321 354
0262720 346 353   Z 303   R 350 334 377 212 321 356 346 353   Z 303 313
0262740 313 313   ` 036 272  \0 220 216 332   3 366 271  \0 200 363 255
0262760 200 356 020   u 362 037   a 313 271 220  \0 350   V  \0   $ 017
=== [/code] ===

but have no idea how to use it...
best regards.


2013/7/25 Stefan Tauner <stefan.tauner@student.tuwien.ac.at>

> On Thu, 25 Jul 2013 21:31:01 +0200
> Stefan Tauner <stefan.tauner@student.tuwien.ac.at> wrote:
>
> > You can also set this somehow with pciset as you know, I am just not
> > entirely sure about the exact commands.
> > you would need to get the gpiobase first with
> > setpci -s 00:1f.0 58.l
> > (only bits 6-15 are the base address see datasheet)
> > and then fetch the old value with
> > setpci -s 0:1f.0 gpiobase+0x0c
> > and set it with
> > setpci -s 0:1f.0 gpiobase+0x0c=...
>
> Actually this can't work out (thanks to Kyösti for pointing that out).
> Because the gpiobase address is in the separated i/o address space of
> the cpu. "The control for the general purpose I/O signals is handled
> through a separate 64-byte I/O space."
> I am not aware of any distributed binaries that work similar to setpci
> but in the i/o space, so you would need to program your own... like the
> one described here:
> http://flashrom.org/Board_Enable
>
> --
> Kind regards/Mit freundlichen Grüßen, Stefan Tauner
>
san - 2013-07-26 23:16:20
I've tried to do reverse program, but it is not for me...

I can share with someone my login, password and address to connect to this
PC via ssh to solve this problem.

Anyone?


2013/7/25 Stefan Tauner <stefan.tauner@student.tuwien.ac.at>

> On Thu, 25 Jul 2013 21:31:01 +0200
> Stefan Tauner <stefan.tauner@student.tuwien.ac.at> wrote:
>
> > You can also set this somehow with pciset as you know, I am just not
> > entirely sure about the exact commands.
> > you would need to get the gpiobase first with
> > setpci -s 00:1f.0 58.l
> > (only bits 6-15 are the base address see datasheet)
> > and then fetch the old value with
> > setpci -s 0:1f.0 gpiobase+0x0c
> > and set it with
> > setpci -s 0:1f.0 gpiobase+0x0c=...
>
> Actually this can't work out (thanks to Kyösti for pointing that out).
> Because the gpiobase address is in the separated i/o address space of
> the cpu. "The control for the general purpose I/O signals is handled
> through a separate 64-byte I/O space."
> I am not aware of any distributed binaries that work similar to setpci
> but in the i/o space, so you would need to program your own... like the
> one described here:
> http://flashrom.org/Board_Enable
>
> --
> Kind regards/Mit freundlichen Grüßen, Stefan Tauner
>
san - 2013-08-13 16:59:38
With patch:

san@flashrom:~/flashrom/P4$ flashrom -V -w P4.rom
flashrom v0.9.6.1-r1704 on Linux 3.5.0-23-generic (i686)
flashrom is free software, get the source code at http://www.flashrom.org

flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian
Command line (3 args): flashrom -V -w P4.rom
Please select a programmer with the --programmer parameter.
Previously this was not necessary because there was a default set.
To choose the mainboard of this computer use 'internal'. Valid choices are:
internal, dummy, nic3com, nicrealtek, gfxnvidia, drkaiser, satasii,
ft2232_spi,
serprog, buspirate_spi, rayer_spi, pony_spi, nicintel, nicintel_spi,
ogp_spi,
satamv, linux_spi, usbblaster_spi.
san@flashrom:~/flashrom/P4$ flashrom -V -w P4.rom --programmer  internal
flashrom v0.9.6.1-r1704 on Linux 3.5.0-23-generic (i686)
flashrom is free software, get the source code at http://www.flashrom.org

flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian
Command line (5 args): flashrom -V -w P4.rom --programmer internal
Calibrating delay loop... OS timer resolution is 13 usecs, 727M loops per
second, 10 myus = 19 us, 100 myus = 2518 us, 1000 myus = 1153 us, 10000
myus = 11277 us, 52 myus = 57 us, OK.
Initializing internal programmer
ERROR: Could not get I/O privileges (Operation not permitted).
You need to be root.
Error: Programmer initialization failed.
san@flashrom:~/flashrom/P4$ sudo flashrom -V -w P4.rom --programmer
internal
[sudo] password for san:
flashrom v0.9.6.1-r1704 on Linux 3.5.0-23-generic (i686)
flashrom is free software, get the source code at http://www.flashrom.org

flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian
Command line (5 args): flashrom -V -w P4.rom --programmer internal
Calibrating delay loop... OS timer resolution is 12 usecs, 512M loops per
second, delay more than 10% too short (got 63% of expected delay),
recalculating... 713M loops per second, 10 myus = 19 us, 100 myus = 3282
us, 1000 myus = 835 us, 10000 myus = 22949 us, 48 myus = 53 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: " "
DMI string system-product-name: " "
DMI string system-version: " "
DMI string baseboard-manufacturer: " "
DMI string baseboard-product-name: "i845E-PC87366"
DMI string baseboard-version: " "
DMI string chassis-type: "Desktop"
W836xx enter config mode worked or we were already in config mode. W836xx
leave config mode had no effect.
Active config mode, unknown reg 0x20 ID: e9.
Please send the output of "flashrom -V" to
flashrom@flashrom.org with W836xx: your board name: flashrom -V
as the subject to help us finish support for your Super I/O. Thanks.
Found chipset "Intel ICH4/ICH4-L" with PCI ID 8086:24c0. Enabling flash
write...
BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
OK.
The following protocols are supported: FWH.
Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x57
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x57
Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xbf, id2
0x57
Found SST flash chip "SST49LF002A/B" (256 kB, FWH) at physical address
0xfffc0000.
Lock status for 0x000000 (size 0x004000) is 01, write locked
Lock status for 0x004000 (size 0x004000) is 00, full access
Lock status for 0x008000 (size 0x004000) is 01, write locked
Lock status for 0x00c000 (size 0x004000) is 00, full access
Lock status for 0x010000 (size 0x004000) is 01, write locked
Lock status for 0x014000 (size 0x004000) is 00, full access
Lock status for 0x018000 (size 0x004000) is 01, write locked
Lock status for 0x01c000 (size 0x004000) is 00, full access
Lock status for 0x020000 (size 0x004000) is 01, write locked
Lock status for 0x024000 (size 0x004000) is 00, full access
Lock status for 0x028000 (size 0x004000) is 01, write locked
Lock status for 0x02c000 (size 0x004000) is 00, full access
Lock status for 0x030000 (size 0x004000) is 01, write locked
Lock status for 0x034000 (size 0x004000) is 00, full access
Lock status for 0x038000 (size 0x004000) is 01, write locked
Lock status for 0x03c000 (size 0x004000) is 00, full access
Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x57
Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x25, id2 0x82,
id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x25, id2 0x82, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1 is
normal flash content, id2 is normal flash content
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1
0xbf, id2 0x57
Found SST flash chip "SST49LF002A/B" (256 kB, FWH).
Lock status for 0x000000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x000000... Lock status for 0x000000 (size
0x004000) is 00, full access
OK
Lock status for 0x004000 (size 0x004000) is 00, full access
Lock status for 0x008000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x008000... Lock status for 0x008000 (size
0x004000) is 00, full access
OK
Lock status for 0x00c000 (size 0x004000) is 00, full access
Lock status for 0x010000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x010000... Lock status for 0x010000 (size
0x004000) is 00, full access
OK
Lock status for 0x014000 (size 0x004000) is 00, full access
Lock status for 0x018000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x018000... Lock status for 0x018000 (size
0x004000) is 00, full access
OK
Lock status for 0x01c000 (size 0x004000) is 00, full access
Lock status for 0x020000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x020000... Lock status for 0x020000 (size
0x004000) is 00, full access
OK
Lock status for 0x024000 (size 0x004000) is 00, full access
Lock status for 0x028000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x028000... Lock status for 0x028000 (size
0x004000) is 00, full access
OK
Lock status for 0x02c000 (size 0x004000) is 00, full access
Lock status for 0x030000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x030000... Lock status for 0x030000 (size
0x004000) is 00, full access
OK
Lock status for 0x034000 (size 0x004000) is 00, full access
Lock status for 0x038000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x038000... Lock status for 0x038000 (size
0x004000) is 00, full access
OK
Lock status for 0x03c000 (size 0x004000) is 00, full access
Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
Reading old flash chip contents... done.
Erasing and writing flash chip... Trying erase function 0...
0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S,
0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S,
0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S,
0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S,
0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S,
0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S,
0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S,
0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S,
0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S,
0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S,
0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S,
0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S,
0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S,
0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S,
0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S,
0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S,
0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S,
0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S,
0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S,
0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S,
0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S,
0x03f000-0x03ffff:EFAILED at 0x0003f015! Expected=0xff, Found=0x20, failed
byte count from 0x0003f000-0x0003ffff: 0xfbc
ERASE FAILED!
Reading current flash chip contents... done. Looking for another erase
function.
Trying erase function 1... 0x000000-0x003fff:S, 0x004000-0x007fff:S,
0x008000-0x00bfff:S, 0x00c000-0x00ffff:S, 0x010000-0x013fff:S,
0x014000-0x017fff:S, 0x018000-0x01bfff:S, 0x01c000-0x01ffff:S,
0x020000-0x023fff:S, 0x024000-0x027fff:S, 0x028000-0x02bfff:S,
0x02c000-0x02ffff:S, 0x030000-0x033fff:S, 0x034000-0x037fff:S,
0x038000-0x03bfff:S, 0x03c000-0x03ffff:EFAILED at 0x0003c000!
Expected=0xff, Found=0xe8, failed byte count from 0x0003c000-0x0003ffff:
0x3e4b
ERASE FAILED!
Looking for another erase function.
No usable erase functions left.
FAILED!
Uh oh. Erase/write failed. Checking if anything changed.
Good. It seems nothing was changed.
Writing to the flash chip apparently didn't do anything.
This means we have to add special support for your board, programmer or
flash
chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or
mail flashrom@flashrom.org, thanks!
-------------------------------------------------------------------------------
You may now reboot or simply leave the machine running.
Restoring PCI config space for 00:1f:0 reg 0x4e



2013/8/3 Maciej Pijanka <maciej.pijanka@agaran.kernel.pl>

> On Sat, 27 Jul 2013, san wrote:
>
> > nie bangla
>
> Bez logów i lspci nikt nie wrzuci tego patcha do flashroma na stałe nawet
> jako
> niesprawdzonego.
>
>
> >
> > 2013/7/26 san <san@plusnet.pl>
> >
> > > właśnie się tym zajmowałem ;)
> > >
> > >
> > > 2013/7/26 Maciej Pijanka <maciej.pijanka@agaran.kernel.pl>
> > >
> > >> On Fri, 26 Jul 2013, san wrote:
> > >>
> > >> > W następnym mailu napisał, ze to jednak nie zadziała.
> > >>
> > >> Imo można sprawdzić, jak nie zadziała, to nie zrobi nic zupełnie.
> > >>
> > >> > 26 lip 2013 13:21, "Maciej Pijanka" <
> maciej.pijanka@agaran.kernel.pl>
> > >> > napisał(a):
> > >> >
> > >> > > On Fri, 26 Jul 2013, san wrote:
> > >> > >
> > >> > > > Yeah, i tried to understand it about three times...
> > >> > > >
> > >> > > > I'll try again, tommorow. Only thing i found is
> > >> > > >
> > >> > >
> > >> > > Trzeba wziąść zródła z SVN, nałożyć łatkę która wysłał 2 maile
> temu
> > >> stefan
> > >> > > (w
> > >> > > załaczniku), skompilować, odpalić z -V zapis (czyli -V -w <plik>)
> > >> > > Plik powinien różnić się od zawartości romu czyli jakiś nowszy
> jest
> > >> > > potrzebny,
> > >> > > bo inaczej test zapisu jest niewiarygodny.
> > >> > >
> > >> > > ponadto potrzebny jest wynik lspci -nnv zeby poprawić łatkę tak by
> > >> działała
> > >> > > tylko dla jednej konkretnej płyty a nie losowych, czyli mogła
> zostać
> > >> > > wrzucona
> > >> > > do zródeł flashroma do repozytorium bo w takiej postaci jak w
> > >> załaczniku
> > >> > > nie
> > >> > > może zostać commitnięta.
> > >> > >
> > >> > > /Cut/
> > >> > >
> > >> > > >
> > >> > > > but have no idea how to use it...
> > >> > > > best regards.
> > >> > > >
> > >> > > >
> > >> > > > 2013/7/25 Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
> > >> > > >
> > >> > > > > On Thu, 25 Jul 2013 21:31:01 +0200
> > >> > > > > Stefan Tauner <stefan.tauner@student.tuwien.ac.at> wrote:
> > >> > > > >
> > >> > > > > > You can also set this somehow with pciset as you know, I am
> > >> just not
> > >> > > > > > entirely sure about the exact commands.
> > >> > > > > > you would need to get the gpiobase first with
> > >> > > > > > setpci -s 00:1f.0 58.l
> > >> > > > > > (only bits 6-15 are the base address see datasheet)
> > >> > > > > > and then fetch the old value with
> > >> > > > > > setpci -s 0:1f.0 gpiobase+0x0c
> > >> > > > > > and set it with
> > >> > > > > > setpci -s 0:1f.0 gpiobase+0x0c=...
> > >> > > > >
> > >> > > > > Actually this can't work out (thanks to Kyösti for pointing
> that
> > >> out).
> > >> > > > > Because the gpiobase address is in the separated i/o address
> > >> space of
> > >> > > > > the cpu. "The control for the general purpose I/O signals is
> > >> handled
> > >> > > > > through a separate 64-byte I/O space."
> > >> > > > > I am not aware of any distributed binaries that work similar
> to
> > >> setpci
> > >> > > > > but in the i/o space, so you would need to program your own...
> > >> like the
> > >> > > > > one described here:
> > >> > > > > http://flashrom.org/Board_Enable
> > >> > > > >
> > >> > > > > --
> > >> > > > > Kind regards/Mit freundlichen Grüßen, Stefan Tauner
> > >> > > > >
> > >> > > >
> > >> > > >
> > >> > > >
> > >> > > > --
> > >> > > > [ e-San.info | San@plusnet.pl ]
> > >> > >
> > >> > > > _______________________________________________
> > >> > > > flashrom mailing list
> > >> > > > flashrom@flashrom.org
> > >> > > > http://www.flashrom.org/mailman/listinfo/flashrom
> > >> > >
> > >> > >
> > >> > > --
> > >> > > Maciej Pijanka
> > >> > > I don't fear computers, I fear lack of them -- Isaac Asimov
> > >> > >
> > >>
> > >> --
> > >> Maciej Pijanka
> > >> I don't fear computers, I fear lack of them -- Isaac Asimov
> > >>
> > >
> > >
> > >
> > > --
> > > [ e-San.info | San@plusnet.pl ]
> > >
> >
> >
> >
> > --
> > [ e-San.info | San@plusnet.pl ]
>
> --
> Maciej Pijanka
> I don't fear computers, I fear lack of them -- Isaac Asimov
>
Stefan Tauner - 2013-08-14 18:04:24
Hello san,

please send the output of lspci -vnn!
I would need to look at our code again but it might be well possible,
that the code added by the patch is never called because of the missing
PCI IDs, so please send the output of lspci.
san - 2013-08-15 13:04:12
sorry, my bad. here it goes:

san@flashrom:~/flashrom/P4$ sudo flashrom -Vnn -w P4.rom --programmer
internal
[sudo] password for san:
flashrom v0.9.6.1-r1704 on Linux 3.5.0-23-generic (i686)
flashrom is free software, get the source code at http://www.flashrom.org

flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian
Command line (5 args): flashrom -Vnn -w P4.rom --programmer internal
Calibrating delay loop... OS timer resolution is 23 usecs, 651M loops per
second, delay more than 10% too short (got 85% of expected delay),
recalculating... 680M loops per second, delay more than 10% too short (got
88% of expected delay), recalculating... 626M loops per second, delay more
than 10% too short (got 82% of expected delay), recalculating... 601M loops
per second, delay more than 10% too short (got 79% of expected delay),
recalculating... 610M loops per second, delay loop is unreliable, trying to
continue 10 myus = 30 us, 100 myus = 86 us, 1000 myus = 1143 us, 10000 myus
= 49282 us, 92 myus = 81 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: " "
DMI string system-product-name: " "
DMI string system-version: " "
DMI string baseboard-manufacturer: " "
DMI string baseboard-product-name: "i845E-PC87366"
DMI string baseboard-version: " "
DMI string chassis-type: "Desktop"
W836xx enter config mode worked or we were already in config mode. W836xx
leave config mode had no effect.
Active config mode, unknown reg 0x20 ID: e9.
Please send the output of "flashrom -V" to
flashrom@flashrom.org with W836xx: your board name: flashrom -V
as the subject to help us finish support for your Super I/O. Thanks.
Found chipset "Intel ICH4/ICH4-L" with PCI ID 8086:24c0. Enabling flash
write...
BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
OK.
The following protocols are supported: FWH.
Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x57
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x57
Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xbf, id2
0x57
Found SST flash chip "SST49LF002A/B" (256 kB, FWH) at physical address
0xfffc0000.
Lock status for 0x000000 (size 0x004000) is 01, write locked
Lock status for 0x004000 (size 0x004000) is 00, full access
Lock status for 0x008000 (size 0x004000) is 01, write locked
Lock status for 0x00c000 (size 0x004000) is 00, full access
Lock status for 0x010000 (size 0x004000) is 01, write locked
Lock status for 0x014000 (size 0x004000) is 00, full access
Lock status for 0x018000 (size 0x004000) is 01, write locked
Lock status for 0x01c000 (size 0x004000) is 00, full access
Lock status for 0x020000 (size 0x004000) is 01, write locked
Lock status for 0x024000 (size 0x004000) is 00, full access
Lock status for 0x028000 (size 0x004000) is 01, write locked
Lock status for 0x02c000 (size 0x004000) is 00, full access
Lock status for 0x030000 (size 0x004000) is 01, write locked
Lock status for 0x034000 (size 0x004000) is 00, full access
Lock status for 0x038000 (size 0x004000) is 01, write locked
Lock status for 0x03c000 (size 0x004000) is 00, full access
Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x57
Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x25, id2 0x82,
id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1
is normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x25, id2 0x82, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x25, id2 0x82, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x25, id2 0x82, id1 is
normal flash content, id2 is normal flash content
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xbf, id2
0x57
Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1
0xbf, id2 0x57
Found SST flash chip "SST49LF002A/B" (256 kB, FWH).
Lock status for 0x000000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x000000... Lock status for 0x000000 (size
0x004000) is 00, full access
OK
Lock status for 0x004000 (size 0x004000) is 00, full access
Lock status for 0x008000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x008000... Lock status for 0x008000 (size
0x004000) is 00, full access
OK
Lock status for 0x00c000 (size 0x004000) is 00, full access
Lock status for 0x010000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x010000... Lock status for 0x010000 (size
0x004000) is 00, full access
OK
Lock status for 0x014000 (size 0x004000) is 00, full access
Lock status for 0x018000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x018000... Lock status for 0x018000 (size
0x004000) is 00, full access
OK
Lock status for 0x01c000 (size 0x004000) is 00, full access
Lock status for 0x020000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x020000... Lock status for 0x020000 (size
0x004000) is 00, full access
OK
Lock status for 0x024000 (size 0x004000) is 00, full access
Lock status for 0x028000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x028000... Lock status for 0x028000 (size
0x004000) is 00, full access
OK
Lock status for 0x02c000 (size 0x004000) is 00, full access
Lock status for 0x030000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x030000... Lock status for 0x030000 (size
0x004000) is 00, full access
OK
Lock status for 0x034000 (size 0x004000) is 00, full access
Lock status for 0x038000 (size 0x004000) is 01, write locked
Trying to clear lock for 0x038000... Lock status for 0x038000 (size
0x004000) is 00, full access
OK
Lock status for 0x03c000 (size 0x004000) is 00, full access
Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
Reading old flash chip contents... done.
Erasing and writing flash chip... Trying erase function 0...
0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S,
0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S,
0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S,
0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S,
0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S,
0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S,
0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S,
0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S,
0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S,
0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S,
0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S,
0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S,
0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S,
0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S,
0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S,
0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S,
0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S,
0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S,
0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S,
0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S,
0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S,
0x03f000-0x03ffff:EFAILED at 0x0003f015! Expected=0xff, Found=0x20, failed
byte count from 0x0003f000-0x0003ffff: 0xfbc
ERASE FAILED!
Reading current flash chip contents... done. Looking for another erase
function.
Trying erase function 1... 0x000000-0x003fff:S, 0x004000-0x007fff:S,
0x008000-0x00bfff:S, 0x00c000-0x00ffff:S, 0x010000-0x013fff:S,
0x014000-0x017fff:S, 0x018000-0x01bfff:S, 0x01c000-0x01ffff:S,
0x020000-0x023fff:S, 0x024000-0x027fff:S, 0x028000-0x02bfff:S,
0x02c000-0x02ffff:S, 0x030000-0x033fff:S, 0x034000-0x037fff:S,
0x038000-0x03bfff:S, 0x03c000-0x03ffff:EFAILED at 0x0003c000!
Expected=0xff, Found=0xe8, failed byte count from 0x0003c000-0x0003ffff:
0x3e4b
ERASE FAILED!
Looking for another erase function.
No usable erase functions left.
FAILED!
Uh oh. Erase/write failed. Checking if anything changed.
Good. It seems nothing was changed.
Writing to the flash chip apparently didn't do anything.
This means we have to add special support for your board, programmer or
flash
chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or
mail flashrom@flashrom.org, thanks!
-------------------------------------------------------------------------------
You may now reboot or simply leave the machine running.
Restoring PCI config space for 00:1f:0 reg 0x4e


Best regards!


2013/8/14 Stefan Tauner <stefan.tauner@student.tuwien.ac.at>

> Hello san,
>
> please send the output of lspci -vnn!
> I would need to look at our code again but it might be well possible,
> that the code added by the patch is never called because of the missing
> PCI IDs, so please send the output of lspci.
>
> --
> Kind regards/Mit freundlichen Grüßen, Stefan Tauner
>

Patch

From cca0945cfaf3d37a031fcbde09a3d98448c811f0 Mon Sep 17 00:00:00 2001
From: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Date: Thu, 25 Jul 2013 21:02:48 +0200
Subject: [PATCH] Add board enable for Pc Partner 845EAS4-262.

Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
---
 board_enable.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/board_enable.c b/board_enable.c
index a4de790..d44721a 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -1680,6 +1680,11 @@  static int intel_ich_gpio18_raise(void)
 	return intel_ich_gpio_set(18, 1);
 }
 
+static int intel_ich_gpio19_lower(void)
+{
+	return intel_ich_gpio_set(19, 0);
+}
+
 /*
  * Suited for:
  *  - MSI MS-7046: LGA775 + 915P + ICH6
@@ -2436,6 +2441,7 @@  const struct board_match board_matches[] = {
 	{0x10DE, 0x0270, 0x1462, 0x7207,  0x10DE, 0x0264, 0x1462, 0x7207, NULL,         NULL, NULL,           P3, "MSI",         "MS-7207 (K8NGM2-L)",    0,   NT, nvidia_mcp_gpio2_raise},
 	{0x10DE, 0x0360, 0x1462, 0x7250,  0x10DE, 0x0368, 0x1462, 0x7250, NULL,         NULL, NULL,           P3, "MSI",         "MS-7250 (K9N SLI)",     0,   OK, nvidia_mcp_gpio2_raise},
 	{0x1011, 0x0019, 0xaa55, 0xaa55,  0x8086, 0x7190,      0,      0, NULL,         NULL, NULL,           P3, "Nokia",       "IP530",                 0,   OK, fdc37b787_gpio50_raise_3f0},
+	{0x8086, 0x1A30,      0,      0,  0x8086, 0x244B,      0,      0, "^i845E-PC87366$", NULL, NULL,      P3, "PC Partner",  "845EAS4-262",           0,   OK, intel_ich_gpio19_lower},
 	{0x8086, 0x24d3, 0x144d, 0xb025,  0x8086, 0x1050, 0x144d, 0xb025, NULL,         NULL, NULL,           P3, "Samsung",     "Polaris 32",            0,   OK, intel_ich_gpio21_raise},
 	{0x1106, 0x3099,      0,      0,  0x1106, 0x3074,      0,      0, NULL,         "shuttle", "ak31",    P3, "Shuttle",     "AK31",                  0,   OK, w836xx_memw_enable_2e},
 	{0x1106, 0x3104, 0x1297, 0xa238,  0x1106, 0x3059, 0x1297, 0xc063, NULL,         NULL, NULL,           P3, "Shuttle",     "AK38N",                 256, OK, NULL},
-- 
Kind regards, Stefan Tauner