From patchwork Thu Jul 25 19:31:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Flashrom fails on write. P4 motherboard Date: Thu, 25 Jul 2013 19:31:01 -0000 From: Stefan Tauner X-Patchwork-Id: 3992 Message-Id: <201307251931.r6PJV2dV032584@mail2.student.tuwien.ac.at> To: san Cc: flashrom@flashrom.org On Thu, 25 Jul 2013 20:23:32 +0200 san wrote: > Just uploaded lspci -nn here: http://e-san.info/Flashrom-P4/lspci-nn.txt > How to lower GPIO by hand (before patch)? Ah I forgot... I need one verbose flag too for the final patch, so that we see the subsystem IDs too, sorry. So it should have been lspci -nnv. I have prepared a preliminary patch that should at least verify if the reverse engineering is correct, see the attachment. You can also set this somehow with pciset as you know, I am just not entirely sure about the exact commands. you would need to get the gpiobase first with setpci -s 00:1f.0 58.l (only bits 6-15 are the base address see datasheet) and then fetch the old value with setpci -s 0:1f.0 gpiobase+0x0c and set it with setpci -s 0:1f.0 gpiobase+0x0c=... I would rather just try the patch. :) Sometimes there happen errors while reverse engineering the code so it is possible that you actually need to raise the pin instead or that the pin number is off by one. If you are a bit into programming then I am sure you can figure out how to refine the patch if necessary, but we can help you too of course. >From cca0945cfaf3d37a031fcbde09a3d98448c811f0 Mon Sep 17 00:00:00 2001 From: Stefan Tauner Date: Thu, 25 Jul 2013 21:02:48 +0200 Subject: [PATCH] Add board enable for Pc Partner 845EAS4-262. Signed-off-by: Stefan Tauner --- board_enable.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board_enable.c b/board_enable.c index a4de790..d44721a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1680,6 +1680,11 @@ static int intel_ich_gpio18_raise(void) return intel_ich_gpio_set(18, 1); } +static int intel_ich_gpio19_lower(void) +{ + return intel_ich_gpio_set(19, 0); +} + /* * Suited for: * - MSI MS-7046: LGA775 + 915P + ICH6 @@ -2436,6 +2441,7 @@ const struct board_match board_matches[] = { {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise}, {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, + {0x8086, 0x1A30, 0, 0, 0x8086, 0x244B, 0, 0, "^i845E-PC87366$", NULL, NULL, P3, "PC Partner", "845EAS4-262", 0, OK, intel_ich_gpio19_lower}, {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, -- Kind regards, Stefan Tauner