Patchwork serialice: Fix a couple of minor typos

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Submitter Mark Marshall
Date 2009-10-14 08:07:43
Message ID <hb40u1$mhb$1@ger.gmane.org>
Download mbox | patch
Permalink /patch/405/
State Not Applicable
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Comments

Mark Marshall - 2009-10-14 08:07:43
Hi.

I've been lurking here for some time, but this is my first post / patch. 
   I'm about to start playing with coreboot a bit and was thinking about 
getting serialice working with the ASUS P2B (I'm interested in this 
vintage of hardware at the moment).

Anyway, as I was looking through the serialice code, I've made these few 
patches, which are minor.

MM
Fix a couple of very minor bugs in serialice:

Correct the type of the parameter 'port' in the function
pnp_set_logical_device.  This should be a u16.  I'm not aware of this
causing a problem with any of the current mainboards as there ports
are all less than 256, but this will cause problems with mainboards
that have there PNP configuration port at 0x3F0.

Correct a comment in serialice.c.  The command "wi" is a write.

Adjust the code saving and restoring eax in start.S.  The code should
save and restore eax around the enqble of FPU and SSE.  If ENABLE_SSE
is defined the value of eax is trashed.  Again, this is mainly cosmetic
as eax is actually never used.

Signed off by:  Mark Marshall
Uwe Hermann - 2009-10-18 02:56:07
On Wed, Oct 14, 2009 at 09:07:43AM +0100, Mark Marshall wrote:
> I've been lurking here for some time, but this is my first post /
> patch.   I'm about to start playing with coreboot a bit and was
> thinking about getting serialice working with the ASUS P2B (I'm
> interested in this vintage of hardware at the moment).

I have a patch for P2B-F somewhere, need to test if that works and then
send in. P2B should be very similar.

 
> Correct the type of the parameter 'port' in the function
> pnp_set_logical_device.  This should be a u16.  I'm not aware of this
> causing a problem with any of the current mainboards as there ports
> are all less than 256, but this will cause problems with mainboards
> that have there PNP configuration port at 0x3F0.

Yep.

 
> Signed off by:  Mark Marshall

The patch was committed as r28, thanks!


Uwe.

Patch

Index: chipset.c
===================================================================
--- chipset.c	(revision 27)
+++ chipset.c	(working copy)
@@ -48,7 +48,7 @@ 
 	outb(value, port + 1);
 }
 
-static inline void pnp_set_logical_device(u8 port, u8 device)
+static inline void pnp_set_logical_device(u16 port, u8 device)
 {
 	pnp_write_register(port, 0x07, device);
 }
Index: serialice.c
===================================================================
--- serialice.c	(revision 27)
+++ serialice.c	(working copy)
@@ -206,7 +206,7 @@ 
 		case (('r' << 8)|'i'): // Read IO *ri
 			serialice_read_io();
 			break;
-		case (('w' << 8)|'i'): // Read IO *wi
+		case (('w' << 8)|'i'): // Write IO *wi
 			serialice_write_io();
 			break;
 		case (('r' << 8)|'c'): // Read CPU MSR *rc
Index: start.S
===================================================================
--- start.S	(revision 27)
+++ start.S	(working copy)
@@ -22,20 +22,22 @@ 
 	.code32
 
 _c_main:
+	movl	%eax, %ebp
+
 	/* Enable FPU registers */
-	movl	%eax, %ebp
 	movl	%cr0, %eax
 	andl	$~(1 << 2), %eax
 	movl	%eax, %cr0
-	movl	%ebp, %eax
 
 #ifdef CONFIG_HAVE_SSE
 	/* enable SSE */
-	movl %cr4, %eax
-	orl $(3<<9), %eax
-	movl %eax, %cr4
+	movl	%cr4, %eax
+	orl	$(3<<9), %eax
+	movl	%eax, %cr4
 #endif
 
+	movl	%ebp, %eax
+
 	/* Setting up the stack (xmmstack only?) */
 	xorl	%esp,%esp
 	movl	$0x7f,%esp #Start address of XMM/MMX stack.