Patchwork Add support for Intel 82599 10G NICs

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Submitter Ed Swierk
Date 2014-12-03 02:18:47
Message ID <1417573127-121117-1-git-send-email-eswierk@skyportsystems.com>
Download mbox | patch
Permalink /patch/4253/
State Accepted
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Comments

Ed Swierk - 2014-12-03 02:18:47
The Intel 82599 series of 10G Ethernet controllers has a bit-banged SPI
interface that's register-compatible with the one in the 1G controllers,
except the register addresses are shifted up by 0x10000.  See
http://www.intel.com/content/www/us/en/ethernet-controllers/82599-10-gbe-controller-datasheet.html.

I tested this with a board that has the 0x10fc device and a Micron M25P40
SPI flash chip.  I filled in device IDs for other 82599 devices per
https://www-ssl.intel.com/content/www/us/en/ethernet-controllers/82599-10-gbe-controller-spec-update.html
and lifted the name strings from the PCI SIG device ID registry.

Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Stefan Tauner - 2014-12-05 22:58:32
On Tue,  2 Dec 2014 18:18:47 -0800
Ed Swierk <eswierk@skyportsystems.com> wrote:

> The Intel 82599 series of 10G Ethernet controllers has a bit-banged SPI
> interface that's register-compatible with the one in the 1G controllers,
> except the register addresses are shifted up by 0x10000.  See
> http://www.intel.com/content/www/us/en/ethernet-controllers/82599-10-gbe-controller-datasheet.html.
> 
> I tested this with a board that has the 0x10fc device and a Micron M25P40
> SPI flash chip.  I filled in device IDs for other 82599 devices per
> https://www-ssl.intel.com/content/www/us/en/ethernet-controllers/82599-10-gbe-controller-spec-update.html
> and lifted the name strings from the PCI SIG device ID registry.
> 
> Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>

Hello Ed,

thank you very much for this patch. I have made some small refinements
to the names and added a few other PCI IDs that seem to make sense (and
actually exist). I have committed the result in r1856.

Patch

===================================================================
diff --git a/trunk/nicintel_spi.c b/trunk/nicintel_spi.c
--- a/trunk/nicintel_spi.c	(revision 1855)
+++ b/trunk/nicintel_spi.c	(working copy)
@@ -80,6 +80,13 @@ 
 	{PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"},
 	{PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"},
 
+	{PCI_VENDOR_ID_INTEL, 0x10f7, NT, "Intel", "10 Gigabit BR KX4 Dual Port Network Connection"},
+	{PCI_VENDOR_ID_INTEL, 0x10f8, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Connection"},
+	{PCI_VENDOR_ID_INTEL, 0x10f9, NT, "Intel", "82599 10 Gigabit Dual Port Network Connection"},
+	{PCI_VENDOR_ID_INTEL, 0x10fb, NT, "Intel", "82599ES 10-Gigabit SFI/SFP+ Network Connection"},
+	{PCI_VENDOR_ID_INTEL, 0x10fc, OK, "Intel", "82599 10 Gigabit Dual Port Network Connection"},
+	{PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit Network Connection"},
+
 	{0},
 };
 
@@ -183,7 +190,13 @@ 
 	if (!io_base_addr)
 		return 1;
 
-	nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE);
+	if (dev->device_id < 0x10f0) {
+		nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr,
+					   MEMMAP_SIZE);
+	} else {
+		nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000,
+					   MEMMAP_SIZE);
+	}
 	if (nicintel_spibar == ERROR_PTR)
 		return 1;