| Submitter | Myles Watson |
|---|---|
| Date | 2009-10-16 21:15:54 |
| Message ID | <2831fecf0910161415o29ca7b7dl4ae498a8b678c151@mail.gmail.com> |
| Download | mbox | patch |
| Permalink | /patch/428/ |
| State | RFC, archived |
| Headers | show |
Comments
I tried it from power on again and I got the same thing. Below is the output after I applied your patch and did a hard reset: coreboot-2.3 Fri Oct 16 15:29:39 MDT 2009 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram2.01 Enabling dual channel memory Registered 166Mhz RAM end at 0x00200000 kB Lower RAM end at 0x00200000 kB Ram3 print_k8regs: func 0 (c0000) 0x40 (Routing 0) 50101 0x44 (Routing 1) 10404 0x60 (Node ID) 10010 print_k8regs: func 1 (c1000) 0x40 (DRAM Base) 3 0x44 (DRAM Lim) 3f0000 0x48 (DRAM Base) 400003 0x4C (DRAM Lim) 7f0001 b8 fc0003 bc ffff00 c0 3 c4 1fff000 e0 3f000003 print_k8regs: func 2 (c2000) nonzero only 40 (DRAM Base) 1 60 (DRAM Base) 3e0fe00 80 (DRAM Base) 4 while waiting for BSP signal to STOP, timeout in ap 01
On Fri, Oct 16, 2009 at 3:37 PM, Hugh Greenberg <hng@lanl.gov> wrote: > I tried it from power on again and I got the same thing. Below is the > output after I applied your patch and did a hard reset: > > coreboot-2.3 Fri Oct 16 15:29:39 MDT 2009 starting... > Enabling routing table for node 00 done. > Enabling SMP settings > (0,1) link=01 > (1,0) link=01 > setup_remote_node: done > Renaming current temporary node to 01 done. > Enabling routing table for node 01 done. > 02 nodes initialized. > coherent_ht_finalize > done > SBLink=00 > NC node|link=00 > entering ht_optimize_link > pos=0x8a, unfiltered freq_cap=0x8075 > pos=0x8a, filtered freq_cap=0x35 > pos=0xce, unfiltered freq_cap=0x35 > freq_cap1=0x35, freq_cap2=0x15 > dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 > dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 > width_cap1=0x11, width_cap2=0x11 > dev1 input ln_width1=0x4, ln_width2=0x4 > dev1 input width=0x1 > dev1 output ln_width1=0x4, ln_width2=0x4 > dev1 input|output width=0x11 > old dev1 input|output width=0x11 > dev2 input|output width=0x11 > old dev2 input|output width=0x11 > entering ht_optimize_link > > pos=0xd2, unfiltered freq_cap=0x35 > pos=0xce, unfiltered freq_cap=0x1 > pos=0xce, filtered freq_cap=0x1 > freq_cap1=0x15, freq_cap2=0x1 > dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 > dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 > width_cap1=0x0, width_cap2=0x0 > dev1 input ln_width1=0x3, ln_width2=0x3 > dev1 input width=0x0 > dev1 output ln_width1=0x3, ln_width2=0x3 > dev1 input|output width=0x0 > old dev1 input|output width=0x0 > dev2 input|output width=0x0 > old dev2 input|output width=0x0 > SMBus controller enabled > Ram1.00 > setting up CPU00 northbridge registers > done. > Ram1.01 > setting up CPU01 northbridge registers > done. > Ram2.00 > Enabling dual channel memory > Registered > 166Mhz > RAM end at 0x00100000 kB > Lower RAM end at 0x00100000 kB > Ram2.01 > Enabling dual channel memory > Registered > 166Mhz > RAM end at 0x00200000 kB > Lower RAM end at 0x00200000 kB > Ram3 > print_k8regs: func 0 (c0000) > 0x40 (Routing 0) 50101 > 0x44 (Routing 1) 10404 > 0x60 (Node ID) 10010 > print_k8regs: func 1 (c1000) > 0x40 (DRAM Base) 3 > 0x44 (DRAM Lim) 3f0000 > 0x48 (DRAM Base) 400003 > 0x4C (DRAM Lim) 7f0001 > b8 fc0003 > bc ffff00 > c0 3 > c4 1fff000 > e0 3f000003 > print_k8regs: func 2 (c2000) nonzero only > 40 (DRAM Base) 1 > 60 (DRAM Base) 3e0fe00 > 80 (DRAM Base) 4 > while waiting for BSP signal to STOP, timeout in ap 01 > Sorry, nothing jumps out at me. Ron's suggestion to remove a processor and see if you get farther will probably get you past this point. Thanks, Myles
On Fri, Oct 16, 2009 at 3:52 PM, Myles Watson <mylesgw@gmail.com> wrote: > Sorry, nothing jumps out at me. Ron's suggestion to remove a processor and > see if you get farther will probably get you past this point. The way I would do this test: 1. take out a CPU and see if it boots 2. Put the CPU in, but put a hack into the code to bypass AP startup. The more data points we have, the better. ron
It didn't work after I took the cpu out. I got the same output. Is there anything else I could try?
Patch
Index: cbv2/src/northbridge/amd/amdk8/debug.c =================================================================== --- cbv2.orig/src/northbridge/amd/amdk8/debug.c +++ cbv2/src/northbridge/amd/amdk8/debug.c @@ -361,4 +361,54 @@ static void dump_mem(unsigned start, uns } print_debug("\r\n"); } -#endif + +static void print_k8regs(void) +{ + device_t k8dev=0; + u32 val; + int i; + + k8dev=PCI_DEV(0,0x18,0); + printk_debug("%s: func 0 (%x)\n", __func__, k8dev); + val = pci_read_config32(k8dev, 0x40); + if (val) + printk_debug("0x40 (Routing 0) %x\n", val); + val = pci_read_config32(k8dev, 0x44); + if (val) + printk_debug("0x44 (Routing 1) %x\n", val); + val = pci_read_config32(k8dev, 0x60); + if (val) + printk_debug("0x60 (Node ID) %x\n", val); + + k8dev=PCI_DEV(0,0x18,1); + printk_debug("%s: func 1 (%x)\n", __func__, k8dev); + val = pci_read_config32(k8dev, 0x40); + if (val) + printk_debug("0x40 (DRAM Base) %x\n", val); + val = pci_read_config32(k8dev, 0x44); + if (val) + printk_debug("0x44 (DRAM Lim) %x\n", val); + val = pci_read_config32(k8dev, 0x48); + if (val) + printk_debug("0x48 (DRAM Base) %x\n", val); + val = pci_read_config32(k8dev, 0x4C); + if (val) + printk_debug("0x4C (DRAM Lim) %x\n", val); + for (i=0x80; i< 0xF0; i+=4) { + val = pci_read_config32(k8dev, i); + if (val) + printk_debug("%x %x\n", i, val); + } + + val = pci_read_config32(k8dev, 0xF0); + if (val) + printk_debug("0xF0 (DRAM Hole) %x\n", val); + + k8dev=PCI_DEV(0,0x18,2); + printk_debug("%s: func 2 (%x) nonzero only \n", __func__, k8dev); + for (i=0x40; i< 0x84; i+=4) { + val = pci_read_config32(k8dev, i); + if (val) + printk_debug("%x (DRAM Base) %x\n", i, val); + } +} Index: cbv2/src/cpu/amd/model_fxx/init_cpus.c =================================================================== --- cbv2.orig/src/cpu/amd/model_fxx/init_cpus.c +++ cbv2/src/cpu/amd/model_fxx/init_cpus.c @@ -342,6 +342,7 @@ static unsigned init_cpus(unsigned cpu_i timeout = wait_cpu_state(bsp_apicid, 0x44); } if(timeout) { + print_k8regs(); print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid); } lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu