| Submitter | coreboot information |
|---|---|
| Date | 2009-10-16 22:30:52 |
| Message ID | <E1MyvK0-0000aa-EZ@ra.coresystems.de> |
| Download | mbox | patch |
| Permalink | /patch/430/ |
| State | Not Applicable |
| Headers | show |
Comments
On 10/16/2009 06:30 PM, coreboot information wrote: > Dear coreboot readers! > > This is the automatic build system of coreboot. > > The developer "rminnich" checked in revision 4796 to > the coreboot repository. This caused the following > changes: > > Change Log: > This is a snapshot as the availability of the systems for this > project is now uncertain, and I can't invest the remaining time > needed to get it done. > > Status is that memory is still not quite configured correctly. It is close > but here are DRAM Row Boundary registers. > Here is coreboot > 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00 > This is close. But: > 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 > is the real hardware. So we are somehow missing those last slots. I think it's > because the SPD connections and the chip connections differ, some dumping > of RAM registers differ. But it's very close. > Hmm, why not try SPD byte 31 to calculate DRB, I use this on the i830 and it has yet to fail. DRB is not hard to calculate it is just the memory size of each row (side) in ticks of 64 in your case. The i830 is similar (except ticks of 32), take a look it may help. > > I want to commit this because even if I get no further, someone else might. > Note that for serialice you need the following temporary patch as well: > Index: src/superio/nsc/pc8374/pc8374_early_init.c > =================================================================== > --- src/superio/nsc/pc8374/pc8374_early_init.c (revision 4791) > +++ src/superio/nsc/pc8374/pc8374_early_init.c (working copy) > @@ -29,7 +29,8 @@ > static void pc8374_enable_dev(device_t dev, unsigned iobase) > { > pnp_set_logical_device(dev); > - pnp_set_enable(dev, 0); > +/* don't disable for now, it kills serialice */ > + pnp_set_enable(dev, 1); > You didn't commit this to real coreboot did you?
Patch
Index: src/superio/nsc/pc8374/pc8374_early_init.c =================================================================== --- src/superio/nsc/pc8374/pc8374_early_init.c (revision 4791) +++ src/superio/nsc/pc8374/pc8374_early_init.c (working copy) @@ -29,7 +29,8 @@ static void pc8374_enable_dev(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); +/* don't disable for now, it kills serialice */ + pnp_set_enable(dev, 1); Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Dear coreboot readers! This is the automatic build system of coreboot. The developer "rminnich" checked in revision 4796 to the coreboot repository. This caused the following changes: Change Log: This is a snapshot as the availability of the systems for this project is now uncertain, and I can't invest the remaining time needed to get it done. Status is that memory is still not quite configured correctly. It is close but here are DRAM Row Boundary registers. Here is coreboot 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00 This is close. But: 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 is the real hardware. So we are somehow missing those last slots. I think it's because the SPD connections and the chip connections differ, some dumping of RAM registers differ. But it's very close. This is under serialice. Once we get to this point we get stuck here: Copying coreboot to RAM. Copying coreboot to RAM. Copying coreboot to RAM. Forever. Here is the total config for 0:0.0 from coreboot: PCI: 00:00.00 00: 86 80 90 35 06 00 90 00 0c 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 60 2a 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00 70: 0a 0a 00 00 00 00 00 00 67 11 5e 55 1e 02 20 2c 80: 41 28 21 00 00 00 00 00 80 01 00 f0 00 00 00 00 90: 00 00 00 00 00 a1 04 39 aa aa 0c 30 5f 08 02 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: 32 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 11 00 c0 ff 03 00 00 df 03 20 00 00 e0 d0: 02 28 00 0e 07 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 36 3c 00 00 00 00 00 00 f0: 00 00 00 00 3a 01 42 00 80 0f 0c 00 00 00 00 00 And from factory: 00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09) 00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 20 6a 00 00 00 00 00 00 10 11 11 01 00 00 10 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c 80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00 90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0 d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 3a 3c 00 00 00 00 00 00 f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00 I want to commit this because even if I get no further, someone else might. Note that for serialice you need the following temporary patch as well: Build Log: Compilation of amd:db800 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4796&device=db800&vendor=amd&num=2 Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4796&device=msm800sev&vendor=digitallogic&num=2 If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system