This is a vx800 mainboard patch based on a different vx800 development
board. The board is referenced as "example board" due to NDA issues.
It contains some board specific things that we may want to fix. The
patch is known to work on real hardware and passes the basic tests:
sound, networking (in XP with a driver), usb, sata, c2c3 in XP, s3,s4,
powerdown. The point of this patch is to "share early and share
often".
Signed-off-by: Bari Ari <bari@onelabs.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
===================================================================
@@ -1205,6 +1205,21 @@
#define PCI_DEVICE_ID_VIA_CN700_VLINK 0x7314
#define PCI_DEVICE_ID_VIA_CN700_BRIDGE 0xB198
#define PCI_DEVICE_ID_VIA_CN700_VGA 0x3344
+#define PCI_DEVICE_ID_VIA_VX800_NB_HOST_BUS 0x2409
+#define PCI_DEVICE_ID_VIA_VX800_NB_HOST_CTRL 0x0409
+#define PCI_DEVICE_ID_VIA_VX800_NB_CTC 0x5409
+//#define PCI_DEVICE_ID_VIA_VX800_LPC 0x8409
+#define PCI_DEVICE_ID_VIA_VX800_LPC 0x8353
+#define PCI_DEVICE_ID_VIA_VX800_VGA 0x5122
+//#define PCI_DEVICE_ID_VIA_VX800_IDE 0xC409
+#define PCI_DEVICE_ID_VIA_VX800_IDE 0x5324
+#define PCI_DEVICE_ID_VIA_VX800_MEMCTRL 0x3409
+#define PCI_DEVICE_ID_VIA_VX800_NB_VLINK 0x7409
+#define PCI_DEVICE_ID_VIA_VX800_SB_VLINK 0xa353
+#define PCI_DEVICE_ID_VIA_VX800_NB_PMU 0x4409
+#define PCI_DEVICE_ID_VIA_VX800_SB_P2P 0xB353
+#define PCI_DEVICE_ID_VIA_VX800_UHCI 0x3038
+#define PCI_DEVICE_ID_VIA_VX800_EHCI 0x3104
#define PCI_DEVICE_ID_VIA_CN400_AGP 0x0259
#define PCI_DEVICE_ID_VIA_CN400_ERR 0x1259
#define PCI_DEVICE_ID_VIA_CN400_HOST 0x2259
===================================================================
@@ -0,0 +1,101 @@
+/* by yhlu 6.2005 */
+/* be warned, this file will be used other cores and core 0 / node 0 */
+static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
+{
+
+ __asm__ volatile (
+ /*
+ FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
+ It is only needed if we want to go back
+ */
+
+ /* We don't need cache as ram for now on */
+ /* disable cache */
+ "movl %cr0, %eax\n\t"
+ "orl $(0x1<<30),%eax\n\t"
+ "movl %eax, %cr0\n\t"
+
+
+ /* Set the default memory type and disable fixed and enable variable MTRRs */
+ "movl $0x2ff, %ecx\n\t"
+ //"movl $MTRRdefType_MSR, %ecx\n\t"
+ "xorl %edx, %edx\n\t"
+ /* Enable Variable and Disable Fixed MTRRs */
+ "movl $0x00000800, %eax\n\t"
+ "wrmsr\n\t"
+
+ /* enable caching for first 1M using variable mtrr */
+ "movl $0x200, %ecx\n\t"
+ "xorl %edx, %edx\n\t"
+ "movl $(0 | 6), %eax\n\t"
+ //"movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
+ "wrmsr\n\t"
+
+/* enable cache 0-7ffff, 80000-9ffff, c0000-fffff;
+if cache 0-1M, then when resume from s3, there is stange color on screen for 2 sec.
+suppose problem of a0000-bfffff.*/
+ "movl $0x201, %ecx\n\t"
+ "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
+ "movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax\n\t"
+ "wrmsr\n\t"
+
+ "movl $0x202, %ecx\n\t"
+ "xorl %edx, %edx\n\t"
+ "movl $(0x80000 | 6), %eax\n\t"
+ "orl $(0 | 6), %eax\n\t"
+ "wrmsr\n\t"
+
+ "movl $0x203, %ecx\n\t"
+ "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
+ "movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax\n\t"
+ "wrmsr\n\t"
+
+ "movl $0x204, %ecx\n\t"
+ "xorl %edx, %edx\n\t"
+ "movl $(0xc0000 | 6), %eax\n\t"
+ "orl $(0 | 6), %eax\n\t"
+ "wrmsr\n\t"
+
+ "movl $0x205, %ecx\n\t"
+ "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
+ "movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax\n\t"
+ "wrmsr\n\t"
+
+ /*cache CONFIG_XIP_ROM_BASE-SIZE to speedup the coreboot code*/
+ "movl $0x206, %ecx\n\t"
+ "xorl %edx, %edx\n\t"
+ "movl $(0xffffffff - CONFIG_ROM_SIZE+ 1),%eax\n\t"
+ "orl $(0 | 6), %eax\n\t"
+ "wrmsr\n\t"
+
+ "movl $0x207, %ecx\n\t"
+ "xorl %edx, %edx\n\t"
+ "movl $CONFIG_ROM_SIZE,%eax\n\t"
+ "decl %eax\n\t"
+ "notl %eax\n\t"
+ "orl $(0 | 0x800), %eax\n\t"
+ "wrmsr\n\t"
+
+ /* enable cache */
+ "movl %cr0, %eax\n\t"
+ "andl $0x9fffffff,%eax\n\t"
+ "movl %eax, %cr0\n\t"
+ "invd\n\t"
+ );
+}
+
+static void disable_cache_as_ram_bsp(void)
+{
+ __asm__ volatile (
+// "pushl %eax\n\t"
+ "pushl %edx\n\t"
+ "pushl %ecx\n\t"
+ );
+
+ disable_cache_as_ram();
+ __asm__ volatile (
+ "popl %ecx\n\t"
+ "popl %edx\n\t"
+// "popl %eax\n\t"
+ );
+}
===================================================================
@@ -0,0 +1,99 @@
+/* 2005.6 by yhlu
+ * 2006.3 yhlu add copy data from CAR to ram
+ */
+#include "cpu/via/car/disable_cache_as_ram.c"
+
+#include "cpu/amd/car/clear_init_ram.c"
+
+static inline void print_debug_pcar(const char *strval, uint32_t val)
+{
+#if CONFIG_USE_PRINTK_IN_CAR
+ printk_debug("%s%08x\r\n", strval, val);
+#else
+ print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
+#endif
+}
+
+static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes)
+{
+ __asm__ volatile(
+ "cld\n\t"
+ "rep; movsl\n\t"
+ : /* No outputs */
+ : "S" (src), "D" (dest), "c" ((bytes)>>2)
+ );
+}
+/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */
+
+static void post_cache_as_ram(void)
+{
+
+#if 1
+ {
+ /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+ unsigned v_esp;
+ __asm__ volatile (
+ "movl %%esp, %0\n\t"
+ : "=a" (v_esp)
+ );
+ print_debug_pcar("v_esp=", v_esp);
+ }
+#endif
+
+ unsigned testx = 0x5a5a5a5a;
+ print_debug_pcar("testx = ", testx);
+
+ /* copy data from cache as ram to
+ ram need to set CONFIG_RAMTOP to 2048*1024 and use var mtrr instead.
+ */
+#if CONFIG_RAMTOP <= 0x100000
+ #error "You need to set CONFIG_RAMTOP greater than 1M"
+#endif
+
+ __asm__ volatile (
+ /* set new esp */ /* before CONFIG_RAMBASE */
+ "subl %0, %%ebp\n\t"
+ "subl %0, %%esp\n\t"
+ ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMTOP)
+ ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
+#if 0
+ __asm__ volatile (
+ "popl %eax\n\t"
+ );
+#endif
+
+
+ /* We can put data to stack again */
+
+ /* only global variable sysinfo in cache need to be offset */
+ print_debug("Done\r\n");
+ print_debug_pcar("testx = ", testx);
+
+ print_debug("Disabling cache as ram now \r\n");
+ disable_cache_as_ram_bsp();
+
+ print_debug("Clearing initial memory region: ");
+ clear_init_ram(); //except the range from [CONFIG_RAMTOP - CONFIG_DCACHE_RAM_SIZE, CONFIG_RAMTOP)
+ print_debug("Done\r\n");
+
+// dump_mem(CONFIG_RAMTOP - 0x8000, CONFIG_RAMTOP - 0x7c00);
+
+#ifndef CONFIG_MEM_TRAIN_SEQ
+#define CONFIG_MEM_TRAIN_SEQ 0
+#endif
+// set_sysinfo_in_ram(1); // So other core0 could start to train mem
+
+#if CONFIG_MEM_TRAIN_SEQ == 1
+// struct sys_info *sysinfox = (CONFIG_RAMTOP - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+ // wait for ap memory to trained
+// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
+#endif
+ /*copy and execute coreboot_ram */
+ copy_and_run();
+ /* We will not return */
+
+ print_debug("should not be here -\r\n");
+
+}
+
===================================================================
@@ -8,8 +8,6 @@
* Copyright (C) 2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
* Copyright (C) 2007,2008 Carl-Daniel Hailfinger
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,7 +27,7 @@
#define CacheBase CONFIG_DCACHE_RAM_BASE
-#include <cpu/x86/mtrr.h>
+#include <cpu/x86/mtrr.h>
/* Save the BIST result */
movl %eax, %ebp
@@ -102,19 +100,22 @@
andl $0x9fffffff,%eax
movl %eax, %cr0
+ cld
+
/* Read the range with lodsl*/
- cld
+ movl CONFIG_XIP_ROM_BASE, %esi
+ movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
+ rep lodsl
+
movl $CacheBase, %esi
- movl %esi, %edi
movl $(CacheSize>>2), %ecx
rep lodsl
- movl $CacheBase, %esi
- movl %esi, %edi
+ movl $CacheBase, %edi
movl $(CacheSize>>2), %ecx
/* 0x5c5c5c5c is a memory test pattern.
- * TODO: Check if everything works with the zero pattern as well. */
+ * TODO: Check if everything works with the zero pattern as well. */
/*xorl %eax, %eax*/
xorl $0x5c5c5c5c,%eax
rep stosl
@@ -125,8 +126,8 @@
rep lodsl
/* The key point of this CAR code is C7 cache does not turn into
- * "no fill" mode, which is not compatible with general CAR code.
- */
+ * "no fill" mode, which is not compatible with general CAR code.
+ */
movl $(CacheBase+CacheSize-4), %eax
movl %eax, %esp
@@ -152,11 +153,11 @@
#endif
/* Restore the BIST result */
- movl %ebp, %eax
+ movl %ebp, %eax
/* We need to set ebp ? No need */
- movl %esp, %ebp
- pushl %eax /* bist */
- call amd64_main
+ movl %esp, %ebp
+ pushl %eax /* bist */
+ call amd64_main
/* We will not go back */
fixed_mtrr_msr:
===================================================================
@@ -60,6 +60,7 @@
0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV
0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV
0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV
+ 0x0406, 0x0609, //
0x0806, 0x0c09, // 800MHz, 796mV --> 1200MHz, 844mV
0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV
0x0806, 0x1010, // 800MHz, 796mV --> 1600MHz, 956mV
@@ -100,6 +101,13 @@
}
}
+#if 1
+ /* Some value may not be included in c7d_speed_translation,
+ so a more general way is needed:*/
+ current=msr.hi&0xffff;
+ msr.lo=msr.lo&0xffff0000;
+ msr.lo=msr.lo|current;
+#else
current = msr.lo & 0xffff;
// Start out with no change.
@@ -129,6 +137,7 @@
msr.lo = new;
msr.hi = 0;
+#endif
printk_debug(" new msr.lo = %x\n", msr.lo);
wrmsr(MSR_IA32_PERF_CTL, msr);
@@ -149,6 +158,12 @@
printk_info("Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
}
+#if CONFIG_HAVE_ACPI_RESUME == 1
+char *lowmem_backup;
+char *lowmem_backup_ptr;
+int lowmem_backup_size;
+#endif
+
static void model_c7_init(device_t dev)
{
u8 brand;
@@ -209,6 +224,11 @@
/* Enable the local cpu apics */
setup_lapic();
+
+ #if CONFIG_HAVE_ACPI_RESUME == 1
+ /*lowmem_backup_size is need by acpi_jump_to_wakeup() in acpi.c, since c7 has no dual core,so set size to 0*/
+ lowmem_backup_size=0;
+ #endif
};
static struct device_operations cpu_dev_ops = {
@@ -224,6 +244,7 @@
{X86_VENDOR_CENTAUR, 0x06A0}, // VIA C7 Esther
{X86_VENDOR_CENTAUR, 0x06A9}, // VIA C7 Esther
{X86_VENDOR_CENTAUR, 0x06D0}, // VIA C7-M
+ {X86_VENDOR_CENTAUR, 0x06F0}, //
{0, 0},
};
===================================================================
@@ -2,7 +2,7 @@
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_HAVE_INIT_TIMER
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
+#default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
if CONFIG_UDELAY_TSC
default CONFIG_HAVE_INIT_TIMER=1
object delay_tsc.o
===================================================================
@@ -0,0 +1,132 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 One Laptop per Child, Association, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
+
+arch i386 end
+driver mainboard.o
+if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_GENERATE_MP_TABLE object mptable.o end
+if CONFIG_GENERATE_ACPI_TABLES
+ #object fadt.o
+ #object dsdt.o
+ #object ssdt.o
+ #object acpi_tables.o # TODO: Enable? Doesn't build yet.
+end
+# these lines maybe noused
+makerule ./failover.E
+ depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+ depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+if CONFIG_USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ makerule ./cache_as_ram_auto.o
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+ end
+ else
+ makerule ./cache_as_ram_auto.inc
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+ end
+ end
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+ldscript /cpu/x86/16bit/entry16.lds
+
+mainboardinit northbridge/via/vx800/romstrap.inc
+ldscript /northbridge/via/vx800/romstrap.lds
+
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/32bit/entry32.lds
+if CONFIG_USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+#mainboardinit arch/i386/lib/cpu_reset.inc
+#here cpu_reset.inc have label _cpu_reset, which is needed in failover,c, but cpu_reset.inc also has code to jump to __main() which is not included in cache_as_ram_auto_auto.c
+
+
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+if CONFIG_USE_DCACHE_RAM
+ mainboardinit cpu/via/car/cache_as_ram.inc
+end
+
+if CONFIG_USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+# failover.inc need defination in cpu_reset.inc, but cpu_reset.inc not included,so ...
+# mainboardinit ./failover.inc
+end
+#mainboardinit cpu/x86/fpu/enable_fpu.inc
+#mainboardinit cpu/x86/mmx/enable_mmx.inc
+
+
+if CONFIG_USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ initobject cache_as_ram_auto.o
+ else
+ mainboardinit ./cache_as_ram_auto.inc
+ end
+end
+
+#mainboardinit cpu/x86/mmx/disable_mmx.inc
+dir /pc80
+
+config chip.h
+
+
+chip northbridge/via/vx800 # Northbridge
+ device pci_domain 0 on
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on end # PCI Bridge
+ #device pci f.0 on end # IDE/SATA
+ #device pci f.1 on end # IDE
+ #device pci 10.0 on end # USB 1.1
+ #device pci 10.1 on end # USB 1.1
+ #device pci 10.2 on end # USB 1.1
+ #device pci 10.4 on end # USB 2.0
+ #device pci 11.0 on # Southbridge LPC
+ #end # pci 11.0
+
+ end # pci domain 0
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/via/model_c7
+ device apic 0 on end # APIC
+ end
+ end
+end
===================================================================
@@ -0,0 +1,135 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 One Laptop per Child, Association, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+uses CONFIG_GENERATE_MP_TABLE
+uses CONFIG_GENERATE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses COREBOOT_EXTRA_VERSION
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_GENERATE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_VIDEO_MB
+uses CONFIG_IOAPIC
+
+##
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_USE_INIT
+uses CONFIG_RAMTOP
+uses CONFIG_GENERATE_ACPI_TABLES
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_HAVE_LOW_TABLES
+
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+
+##
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xffef0000
+#default CONFIG_DCACHE_RAM_BASE=0xffbf0000
+#default CONFIG_DCACHE_RAM_BASE=0xfec00000 //hpet may use this
+default CONFIG_DCACHE_RAM_SIZE=0x2000
+default CONFIG_USE_INIT=0
+# More 1M for pgtbl.
+## default CONFIG_GENERATE_ACPI_TABLES = 1 # FIXME: Doesn't build yet.
+default CONFIG_GENERATE_ACPI_TABLES = 0
+default CONFIG_HAVE_MAINBOARD_RESOURCES = 1
+default CONFIG_HAVE_LOW_TABLES = 0
+## default CONFIG_HAVE_ACPI_RESUME = 1
+default CONFIG_HAVE_ACPI_RESUME = 0 # FIXME: Doesn't build yet.
+
+default CONFIG_MAINBOARD_VENDOR = "VIA"
+default CONFIG_MAINBOARD_PART_NUMBER = "vx800ex"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1106
+# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
+
+
+default CONFIG_ROM_SIZE = 512 * 1024
+default CONFIG_IOAPIC = 1
+
+#define framebuffer size integrated graphics card. support 32 64 128 256
+default CONFIG_VIDEO_MB = 64
+
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default CONFIG_PCI_ROM_RUN = 0
+default CONFIG_CONSOLE_VGA = 0
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_GENERATE_MP_TABLE = 0
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+default CONFIG_HAVE_HARD_RESET = 0
+default CONFIG_GENERATE_PIRQ_TABLE = 0
+default CONFIG_IRQ_SLOT_COUNT = 10
+default CONFIG_HAVE_OPTION_TABLE = 1
+default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_USE_FALLBACK_IMAGE = 1
+default CONFIG_STACK_SIZE = 16 * 1024
+default CONFIG_HEAP_SIZE = 20 * 1024
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+# More 1M for pgtbl.
+default CONFIG_RAMTOP = 32768 * 1024
+# to 1MB
+default CONFIG_RAMBASE = 0x1F00000
+default CONFIG_ROM_PAYLOAD = 1
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CROSS_COMPILE)gcc -m32"
+default HOSTCC = "gcc"
+
+end
+
===================================================================
@@ -0,0 +1,193 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <../../../northbridge/via/vx800/vx800.h>
+
+extern unsigned char AmlCode_dsdt[];
+extern unsigned char AmlCode_ssdt[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /*no pci-e in chipset, but there is a mmconfig_BAR in d0f5, so... */
+ device_t dev;
+ struct resource *res;
+ dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800_NB_CTC, 0);
+ if (!dev)
+ return current;
+
+ res = find_resource(dev, VX800_D0F5_MMCONFIG_MBAR);
+ if (res) {
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
+ current, res->base, 0x0, 0x0, 0x04);
+ }
+ return current;
+}
+
+
+unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
+{
+ device_t cpu;
+ int cpu_index = 0;
+
+ for(cpu = all_devices; cpu; cpu = cpu->next) {
+ if ((cpu->path.type != DEVICE_PATH_APIC) ||
+ (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
+ continue;
+ }
+ if (!cpu->enabled) {
+ continue;
+ }
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
+ cpu_index++;
+ }
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ unsigned int gsi_base = 0x18;
+
+ /* Create all subtables for processors. */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB IOAPIC. */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ VX800_APIC_SB_ID, VX800_APIC_SB_BASE, 0);
+
+ /* IRQ0 -> APIC IRQ2. */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0x0);
+
+ /* IRQ9 ACPI active low. */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+
+ /* Create all subtables for processors. */
+ current = acpi_create_madt_lapic_nmis(current,
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
+
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+}
+
+#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_srat_t *srat;
+ acpi_rsdt_t *rsdt;
+ acpi_mcfg_t *mcfg;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+
+ /* Align ACPI tables to 16byte */
+ start = ( start + 0x0f ) & -0x10;
+ current = start;
+
+ printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk_debug("ACPI: * FACS\n");
+ current = ALIGN(current, 64);
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ printk_debug("ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ current += ((acpi_header_t *)AmlCode_dsdt)->length;
+ memcpy((void *)dsdt,(void *)AmlCode_dsdt, ((acpi_header_t *)AmlCode_dsdt)->length);
+ dsdt->checksum = 0; /* don't trust intel iasl compiler to get this right. */
+ dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
+ printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length);
+
+ printk_debug("ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt,facs,dsdt);
+ acpi_add_table(rsdt,fadt);
+
+ /* If we want to use HPET timers Linux wants it in MADT. */
+ printk_debug("ACPI: * MADT\n");
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdt, madt);
+
+ printk_debug("ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ acpi_add_table(rsdt, mcfg);
+
+
+ printk_debug("ACPI: * HPET\n");
+ hpet = (acpi_mcfg_t *) current;
+ acpi_create_hpet(hpet);
+ current += hpet->header.length;
+ acpi_add_table(rsdt, hpet);
+
+ /*printk_debug("ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *) current;
+ current += ((acpi_header_t *)AmlCode_ssdt)->length;
+ memcpy((void *)ssdt,(void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
+ ssdt->checksum = 0; // don't trust intel iasl compiler to get this right
+ ssdt->checksum = acpi_checksum(ssdt, ssdt->length);
+ acpi_add_table(rsdt, ssdt);
+ printk_debug("ACPI: * SSDT @ %08x Length %x\n", ssdt, ssdt->length);
+ */
+ printk_info("ACPI: done.\n");
+ return current;
+}
===================================================================
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+ #include "northbridge/via/vx800/driving_clk_phase_data.h"
+
+// DQS Driving
+//Reg0xE0, 0xE1
+// According to #Bank to set DRAM DQS Driving
+// #Bank 1 2 3 4 5 6 7 8
+static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE};
+static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE};
+
+// DQ Driving
+//Reg0xE2, 0xE3
+// For DDR2: According to bank to set DRAM DQ Driving
+static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC };
+static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA };
+
+
+// CS Driving
+//Reg0xE4, 0xE5
+// According to #Bank to set DRAM CS Driving
+// DDR1 #Bank 1 2 3 4 5 6 7 8
+static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 };
+static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44};
+static const u8 DDR2_CSA_Driving_Table_x16[4]= { 0x44, 0x44, 0x44, 0x44};
+static const u8 DDR2_CSB_Driving_Table_x16[2]= { 0x44, 0x44};
+// MAA Driving
+//Reg0xE8, Reg0xE9
+static const u8 DDR2_MAA_Driving_Table[MA_Table][5] =
+ {
+ //Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8
+ { 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06
+ { 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18
+ {255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~
+ };
+
+static const u8 DDR2_MAB_Driving_Table[MA_Table][2] =
+ {
+ // Chip number, Value ;(SRAS, SCAS, SWE)RxE9
+ { 6, 0x86 }, // total MAB chips = 00 ~ 06
+ { 18, 0x86 }, // total MAB chips = 06 ~ 18
+ {255, 0xDB } // total MAB chips = 18 ~
+ };
+
+// DCLK Driving
+//Reg0xE6, 0xE7
+// For DDR2: According to #Freq to set DRAM DCLK Driving
+// freq 400M, 533M, 667M, 800M
+
+static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
+static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
+
+/*
+Duty cycle
+Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB
+D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF
+According to DRAM frequency to control Duty Cycle
+*/
+static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] =
+ {
+ // (And NOT) DDR800 DDR667 DDR533 DDR400
+ //Reg Mask Value Value Value Value
+ {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank
+ {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 },
+ {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30}
+ };
+
+static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] =
+ {
+ // (And NOT) DDR800 DDR667 DDR533 DDR400
+ //Reg Mask Value Value Value Value
+ {0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank
+ {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 },
+ {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 }
+ };
+
+
+/*
+DRAM Clock Phase Control for FeedBack Mode
+Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94
+Processing:
+ 1.Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode
+ 2.Program clock phase value with ChA/B DCLK enable, VIA_NB3DRAM_REG91[7:3]=00b
+ 3.Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO
+ ChA DCLKO can not be disable, so always program VIA_NB3DRAM_REG91[3]=0b
+ */
+static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] =
+ {
+ // (And NOT) DDR800 DDR667 DDR533 DDR400
+ //Reg Mask Value Value Value Value
+ {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank
+ {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 },
+ {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 }
+ };
+
+static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] =
+ {
+ // (And NOT) DDR800 DDR667 DDR533 DDR400
+ //Reg Mask Value Value Value Value
+ {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank
+ {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 },
+ {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 }
+ };
+
+static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] =
+ {
+ // (And NOT) DDR800 DDR667 DDR533 DDR400
+ //Reg Mask Value Value Value Value
+ {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank
+ {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 },
+ {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 }
+ };
+
+static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
+ {
+ // (And NOT) DDR800 DDR667 DDR533 DDR400
+ //Reg Mask Value Value Value Value
+ {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank
+ {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 },
+ {0x76, 0x10, 0x80, 0x87, 0x07, 0x06 },
+ {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 }
+ };
+
+/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
+ {
+ // (And NOT) DDR800 DDR667 DDR533 DDR400
+ //Reg Mask Value Value Value Value
+ {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank
+ {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 },
+ {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 }
+ };
+*/
+/*
+DQ/DQS Output Delay Control
+Modify NB D0F3: RxF0/RxF1/RxF2/RxF3
+*/
+static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] =
+ {
+ // RxF0 RxF1 RxF2 RxF3
+ { 0x00, 0x00, 0x00, 0x00 },// DDR400
+ { 0x00, 0x00, 0x00, 0x00 },// DDR533
+ { 0x00, 0x00, 0x00, 0x00 },// DDR667
+ { 0x00, 0x00, 0x00, 0x00 }// DDR800
+ };
+static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] =
+ {
+ // RxF4 RxF5 RxF6 RxF7
+ { 0x00, 0x00, 0x00, 0x00 },// DDR400
+ { 0x00, 0x00, 0x00, 0x00 },// DDR533
+ { 0x00, 0x00, 0x00, 0x00 },// DDR667
+ { 0x00, 0x00, 0x00, 0x00 }// DDR800
+ };
+static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
+ {
+ // (And NOT) DDR800 DDR667 DDR533 DDR400
+ //Reg Mask Value Value Value Value
+ {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank
+ {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
+ {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 }
+ };
+
+static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
+ {
+ // (And NOT) DDR800 DDR667 DDR533 DDR400
+ //Reg Mask Value Value Value Value
+ {0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank
+ {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 },
+ {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 }
+ };
+
+static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] =
+{
+// Rx70 Rx71
+ { 0x00, 0x05 }, // DDR800
+ { 0x00, 0x06 }, // DDR667
+ { 0x00, 0x04 }, // DDR533
+ { 0x00, 0x05 } // DDR400
+};
+static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] =
+{
+// Rx70 Rx71
+ {0x00 , 0x04}, // DDR800
+ {0x00 , 0x04}, // DDR667
+ {0x00 , 0x03}, // DDR533
+ {0x00 , 0x04} // DDR400
+};
===================================================================
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+};
===================================================================
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <boot/tables.h>
+#include "chip.h"
+#include <../../../northbridge/via/vx800/vx800.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ CONFIG_RAMBASE, (CONFIG_RAMTOP - CONFIG_RAMBASE));
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE);
+ #endif
+
+ device_t dev;
+ uint8_t data8;
+ uint32_t data32;
+ dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800_NB_CTC, 0);
+ data8=pci_read_config8(dev, 0x60);
+ data8=data8&0x03;
+ if(data8==0x03){
+ data8=pci_read_config8(dev, VX800_D0F5_MMCONFIG_MBAR);
+ data32=data8<<28;
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ data32,0x10000000);
+ }
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA vx800example Mainboard")
+};
===================================================================
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
===================================================================
@@ -0,0 +1,293 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "lib/ramtest.c"
+#include "northbridge/via/vx800/vx800.h"
+#include "cpu/x86/bist.h"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+
+#include "northbridge/via/vx800/vx800_early_serial.c"
+
+#include <cpu/x86/mem.h>
+#include "cpu/amd/car/copy_and_run.c"
+#include <cpu/x86/mtrr.h>
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/via/car/post_cache_as_ram.c"
+#include "northbridge/via/vx800/vx800_pci_io_modify_ops_for_auto.c"
+#include "mainboard/via/vx800example/dram_driving_clk_phase_data.c"
+#include "northbridge/via/vx800/dram_init.c"
+
+int acpi_is_wakeup_early_via_vx800(void)
+{
+ device_t dev;
+ u16 tmp,result;
+
+ print_debug("In acpi_is_wakeup_early_via_vx800\r\n");
+ // Power management controller
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX800_LPC), 0);
+
+ if (dev == PCI_DEV_INVALID)
+ die("Power management controller not found\r\n");
+
+ // Set ACPI base address to I/O VX800_ACPI_IO_BASE.
+ pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
+
+ // Enable ACPI accessm RTC signal gated with PSON.
+ pci_write_config8(dev, 0x81, 0x84);
+
+ tmp = inw(VX800_ACPI_IO_BASE + 0x04);
+ result= ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
+ print_debug(" boot_mode=");
+ print_debug_hex16(result);
+ print_debug("\r\n");
+ return result ;
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+
+static void enable_mainboard_devices(void)
+{
+ device_t dev;
+ uint16_t values;
+
+ /* Enable multifunction for northbridge.*/
+ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
+
+ /*Enable P2P Bridge Header for External PCI BUS.*/
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800_SB_VLINK), 0);
+ pci_write_config8(dev, 0x4f, 0x41);
+
+ /* 1. D15F0
+ a) RxBAh = 71h
+ b) RxBBh = 05h
+ c) RxBEh = 71h
+ d) RxBFh = 05h
+ 2. D17F0
+ a) RxA0h = 06h
+ b) RxA1h = 11h
+ c) RxA2h = 27h
+ d) RxA3h = 32h
+ e) Rx79h = 40h
+ f) Rx72h = 27h
+ g) Rx73h = 32h
+ */
+ u8 Data8;
+ pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA,
+ PCI_DEVICE_ID_VIA_VX800_IDE);
+ pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE,
+ PCI_DEVICE_ID_VIA_VX800_IDE);
+ pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA);
+ pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2,
+ PCI_DEVICE_ID_VIA_VX800_LPC);
+ Data8=pci_read_config8(PCI_DEV(0, 0x11, 0),0x79);
+ Data8 &= ~0x40;
+ Data8 |=0x40;
+ pci_write_config8(PCI_DEV(0, 0x11, 0),0x79,Data8);
+ pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72,
+ PCI_DEVICE_ID_VIA_VX800_LPC);
+
+ /*enable all device controlled by LPC,include ide, all usb, and others*/
+ pci_modify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x7E, 0x00);
+ pci_modify_config8(PCI_DEV(0, 0x11, 0), 0x51, 0xD0, 0x00);
+ /*close CE-ATA (Consumer Electronics-ATA) and NFC*/
+ pci_modify_config8(PCI_DEV(0, 0x11, 0), 0x51, 0x40, 0x40);
+ /*close USB Device Mode*/
+ pci_modify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x40, 0x40);
+}
+
+static void enable_shadow_ram(void)
+{
+ uint8_t shadowreg;
+ pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
+ // 0xf0000-0xfffff - ACPI tables
+ shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
+ shadowreg |= 0x30;
+ pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
+ /* 0xe0000-0xeffff - elfload? */
+ pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff);
+
+ /*ROM Shadow Control registers in D17F7*/
+ pci_write_config8(PCI_DEV(0, 17, 7), 0x61, 0xff);//same with d0f3Rx80
+ shadowreg = pci_read_config8(PCI_DEV(0, 17, 7), 0x63);
+ shadowreg |= 0xf0;
+ pci_write_config8(PCI_DEV(0, 17, 7), 0x63, shadowreg);//same with d0f3Rx83
+ pci_write_config8(PCI_DEV(0, 17, 7), 0x64, 0xff);//same with d0f3Rx82
+}
+
+struct PCI_REG_INIT_TABLE {
+ u8 ChipRevisionStart;
+ u8 ChipRevisionEnd;
+ u8 Bus;
+ u8 Device;
+ u8 Function;
+ u32 Register;
+ u8 Mask;
+ u8 Value;
+};
+
+/*
+this table contains the value needed to be set before begin to init dram.
+Note: REV_Bx should be cared when porting a new board!!!!! */
+static const struct PCI_REG_INIT_TABLE mNbStage1InitTbl[]= {
+ // Set Exxxxxxx as pcie mmio config range
+ 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E,
+ 0x00, 0xFF, NB_APIC_REG(0x60), 0xEC, 0x13, // Support extended cfg address of pcie
+
+ //0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control
+ // Set ROMSIP value by software
+
+ /*0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3
+ 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3
+ 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3
+ 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3
+ 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl
+ 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl
+ 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit
+ 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status
+ 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset
+ 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset
+ 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status
+ 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status
+ 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group
+ 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group
+ 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group
+ 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus)
+ 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+ 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+ 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+ 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+ 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1
+ 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2
+ 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB
+ 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD
+ 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0)
+ 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1)
+ 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2)
+ 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3)*/
+
+ // CPU Host Bus Control
+ 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
+ //0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
+ 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
+ 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance
+ //0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
+ 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK
+ 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access
+ //0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2
+ 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2
+ 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1
+ //0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
+ //0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2
+ 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy
+ 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer
+ 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl
+ // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3
+ //0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2
+ 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2
+ 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3
+ 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4
+ // Set APIC and SMRAM
+ 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control
+ 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
+ 0x00, 0xFF, 0x00, 0x00, 0x00,0x00, 0x00, 0x00 // End of the table
+};
+
+void pci_inittable(u8 chipversion,struct PCI_REG_INIT_TABLE* initdata)
+{
+ u8 i=0;
+ device_t dev;
+ for(i=0;;i++) {
+ if((initdata[i].Mask==0)&&(initdata[i].Value==0)&&(initdata[i].Bus==0)&&(initdata[i].ChipRevisionEnd==0xff)&&(initdata[i].ChipRevisionStart==0)&&(initdata[i].Device==0)&&(initdata[i].Function==0)&&(initdata[i].Register==0))
+ break;
+ if((chipversion>=initdata[i].ChipRevisionStart)&&(chipversion<=initdata[i].ChipRevisionEnd)){
+ dev=PCI_DEV(initdata[i].Bus,initdata[i].Device,initdata[i].Function);
+ pci_modify_config8(dev, initdata[i].Register,initdata[i].Mask,initdata[i].Value);
+ }
+ }
+}
+
+/* cache_as_ram.inc jump to here
+*/
+void amd64_main(unsigned long bist)
+{
+ unsigned cpu_reset = 0;
+ u16 boot_mode;
+
+ enable_mainboard_devices();
+
+ /* decide if this is a s3 wakeup or a normal boot */
+ boot_mode=acpi_is_wakeup_early_via_vx800();
+ /* transfer "cpu restart" to "cold boot"
+ When this boot is not a S3 resume, and PCI registers had been written,
+ then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */
+ if((boot_mode!=3)&&(pci_read_config8(PCI_DEV(0, 0, 3), 0x80)!=0)) {
+ outb(6, 0xcf9); //x86 cold boot I/O cmd
+ }
+
+ enable_vx800_serial();
+
+ console_init();//src/arch/i386/lib/console
+
+ /* Halt if there was a built-in self test failure. */
+ report_bist_failure(bist);
+
+ u8 Data;
+ device_t dev;
+ /* Get NB Chip revision from D0F4RxF6, revision will be used in via_pci_inittable */
+ dev=PCI_DEV(0, 0, 4);
+ Data=pci_read_config8(dev,0xf6);
+ print_debug("NB chip revision =");
+ print_debug_hex8(Data);
+ print_debug("\r\n");
+ //make NB ready before draminit
+ pci_inittable(Data,mNbStage1InitTbl);
+
+ enable_smbus();
+
+ ddr2_ram_setup();
+
+ enable_shadow_ram();
+
+ post_cache_as_ram();
+
+ print_debug("should not be here -\r\n");
+}
===================================================================
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef VX800_PCI_IO_MODIFY_OPS_C
+#define VX800_PCI_IO_MODIFY_OPS_C 1
+#include <device/pci.h>
+#include <arch/io.h>
+#include "vx800_pci_io_modify_ops_for_auto.c"
+#endif
===================================================================
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef VX800_PCI_IO_MODIFY_OPS_H
+#define VX800_PCI_IO_MODIFY_OPS_H 1
+void pci_modify_config8(device_t dev, unsigned where,u8 mask,u8 orval);
+void pci_modify_config16(device_t dev, unsigned where,uint16_t mask,uint16_t orval);
+void pci_modify_config32(device_t dev, unsigned where, uint32_t mask,uint32_t orval);
+void io_modify_config8(u16 where, uint8_t mask,uint8_t orval);
+#endif
===================================================================
@@ -25,244 +25,78 @@
#include "chip.h"
#include <arch/io.h>
#include "vx800.h"
+#include "vx800_pci_io_modify_ops.h"
-static const idedevicepcitable[16 * 12] = {
- /*
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6,
- 0x00, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0xC2, 0xF9, 0x01, 0x10, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- */
-
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0x99, 0x20, 0xf0, 0x00, 0x00, 0x20,
- 0x00, 0x00, 0x17, 0xF1, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0xc2, 0x09, 0x01, 0x10, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* Legacy BIOS XP PCI value */
- /*
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0xa8, 0x20, 0x00, 0x00, 0x00, 0xb6,
- 0x00, 0x00, 0x16, 0xF1, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0x02, 0x09, 0x00, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- */
-
- /* ROM legacy BIOS on cn_8562b */
- /*
- 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0x99, 0x20, 0x60, 0x00, 0x00, 0x20,
- 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- */
-
- /* From legacy BIOS on c7_8562b */
- /*
- 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0x5E, 0x20, 0x60, 0x00, 0x00, 0xB6,
- 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- */
+static const idedevicepcitable [16*12]={
+0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x99, 0x20, 0xf0, 0x00, 0x00, 0x20,
+0x00, 0x00, 0x17, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
+0x00, 0xc2, 0x09, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
-
static void ide_init(struct device *dev)
{
- uint8_t enables, Rx89, RxC0;
- u8 i, data;
- struct ATA_REG_INIT_TABLE *pEntry;
+ uint8_t enables,Rx89,RxC0;
+ u8 i,data;
+ struct ATA_REG_INIT_TABLE *pEntry;
printk_info("ide_init\n");
+
+ pci_modify_config8(dev, 0x45, 0x00, 0x80);
+ pci_modify_config8(dev, 0x0A, 0x01, 0xFF);
+ pci_modify_config8(dev, 0x45, 0x80, 0x00);
+ pci_modify_config8(dev, 0x40, 0x02, 0x00);
+
+ pci_modify_config8(dev, 0x09, 0x00, 0x05);//COMPATIBLE MODE
+ //pci_modify_config8(dev, 0x09, 0x05, 0x05);//native MODE
-#if 1
- /*these 3 lines help to keep interl back door for DID VID SUBID untouched */
- u16 data16_1, data16_2;
- data16_1 = pci_read_config16(dev, 0xba);
- data16_2 = pci_read_config16(dev, 0xbe);
-
- for (i = 0; i < (16 * 12); i++) {
- pci_write_config8(dev, 0x40 + i, idedevicepcitable[i]);
+ pci_modify_config8(dev, 0x04, 0x00, 0x07);
+
+ #if 1
+ /*these 3 lines help to keep interl back door for DID VID SUBID unchanged*/
+ u16 data16_1,data16_2;
+ data16_1=pci_read_config16(dev,0xba);
+ data16_2=pci_read_config16(dev,0xbe);
+
+ for(i=0;i<(16*12);i++){
+ pci_write_config8(dev, 0x40+i, idedevicepcitable[i]);
}
//pci_write_config8(dev, 0x0d, 0x20);
- data = pci_read_config8(dev, 0x0d);
- data &= 0x0f;
- data |= 0x40;
+ data=pci_read_config8(dev,0x0d);
+ data &=0x0f;
+ data |=0x40;
pci_write_config8(dev, 0x0d, data);
- //these 2 lines help to keep interl back door for DID VID SUBID untouched
+ //these 2 lines help to keep interl back door for DID VID SUBID unchanged
pci_write_config16(dev, 0xba, data16_1);
pci_write_config16(dev, 0xbe, data16_2);
#endif
/* Force interrupts to use compat mode. */
pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
-#if 0
-
- struct southbridge_via_vt8237r_config *sb =
- (struct southbridge_via_vt8237r_config *)dev->chip_info;
-
- u8 enables;
- u32 cablesel;
-
- pci_write_config16(dev, 0x04, 0x0007);
-
- enables = pci_read_config8(dev, IDE_CS) & ~0x3;
- enables |= 0x02;
- pci_write_config8(dev, IDE_CS, enables);
- enables = pci_read_config8(dev, IDE_CS);
- printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
-
- /* Enable only compatibility mode. */
- enables = pci_read_config8(dev, IDE_CONF_II);
- enables &= ~0xc0;
- pci_write_config8(dev, IDE_CONF_II, enables);
- enables = pci_read_config8(dev, IDE_CONF_II);
- printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
-
- /* Enable prefetch buffers. */
- enables = pci_read_config8(dev, IDE_CONF_I);
- enables |= 0xf0;
- pci_write_config8(dev, IDE_CONF_I, enables);
-
- /* Flush FIFOs at half. */
- enables = pci_read_config8(dev, IDE_CONF_FIFO);
- enables &= 0xf0;
- enables |= (1 << 2) | (1 << 0);
- pci_write_config8(dev, IDE_CONF_FIFO, enables);
-
- /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */
- enables = pci_read_config8(dev, IDE_MISC_I);
- enables &= 0xe2;
- enables |= (1 << 4) | (1 << 3);
- pci_write_config8(dev, IDE_MISC_I, enables);
-
- /* Use memory read multiple, Memory-Write-and-Invalidate. */
- enables = pci_read_config8(dev, IDE_MISC_II);
- enables |= (1 << 2) | (1 << 3);
- pci_write_config8(dev, IDE_MISC_II, enables);
-
- /* Force interrupts to use compat mode. */
- pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
- pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
-
- /* Cable guy... */
- cablesel = pci_read_config32(dev, IDE_UDMA);
- cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4));
- cablesel |= (sb->ide0_80pin_cable << 28) |
- (sb->ide0_80pin_cable << 20) |
- (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4);
- pci_write_config32(dev, IDE_UDMA, cablesel);
-#endif
}
+void ide_enable(device_t dev)
+{
+ pci_modify_config8(dev, 0xB9, 0x01, 0x01);
+}
static struct device_operations ide_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = ide_init,
- .enable = 0,
- .ops_pci = 0,
+ .init = ide_init,
+ .enable = ide_enable,
+ .ops_pci = 0,
};
static struct pci_driver via_ide_driver __pci_driver = {
- .ops = &ide_ops,
+ .ops = &ide_ops,
.vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_VX855_IDE,
+ .device = PCI_DEVICE_ID_VIA_VX800_IDE,
};
===================================================================
@@ -41,26 +41,26 @@
u8 acpi_sleep_type = 0;
static void memctrl_init(device_t dev)
-{
+{
/*
- set VGA in uma_ram_setting.c, not in this function.
+ set VGA in uma_ram_setting.c, not in this function.
*/
#if 0
pci_write_config8(dev, 0x85, 0x20);
pci_write_config8(dev, 0x86, 0x2d);
-
+
/* Set up VGA timers */
pci_write_config8(dev, 0xa2, 0x44);
-
+
/* Enable VGA with a 32mb framebuffer */
pci_write_config16(dev, 0xa0, 0xd000);
-
+
pci_write_config16(dev, 0xa4, 0x0010);
-
+
//b0: 60 aa aa 5a 0f 00 00 00 08
pci_write_config16(dev, 0xb0, 0xaa00);
pci_write_config8(dev, 0xb8, 0x08);
-#endif
+#endif
}
static const struct device_operations memctrl_operations = {
@@ -71,22 +71,22 @@
static const struct pci_driver memctrl_driver __pci_driver = {
.ops = &memctrl_operations,
.vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL,
+ .device = PCI_DEVICE_ID_VIA_VX800_MEMCTRL,
};
static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
+ unsigned long basek, unsigned long sizek)
{
- struct resource *resource;
+ struct resource *resource;
- if (!sizek) {
- return;
- }
- resource = new_resource(dev, index);
- resource->base = ((resource_t) basek) << 10;
- resource->size = ((resource_t) sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ if (!sizek) {
+ return;
+ }
+ resource = new_resource(dev, index);
+ resource->base = ((resource_t)basek) << 10;
+ resource->size = ((resource_t)sizek) << 10;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)
@@ -106,8 +106,7 @@
struct resource *min;
u32 tolm;
min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
- tolm_test, &min);
+ search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
@@ -116,21 +115,26 @@
return tolm;
}
+#if CONFIG_WRITE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
static void pci_domain_set_resources(device_t dev)
{
/*
* the order is important to find the correct ram size.
*/
- u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
+ u8 ramregs[] = {0x43, 0x42, 0x41, 0x40};
device_t mc_dev;
- u32 pci_tolm;
+ u32 pci_tolm;
u8 reg;
-
+
printk_spew("Entering vx800 pci_domain_set_resources.\n");
- pci_tolm = find_pci_tolm(&dev->link[0]);
- mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
+ pci_tolm = find_pci_tolm(&dev->link[0]);
+ mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX800_MEMCTRL, 0);
if (mc_dev) {
unsigned long tomk, tolmk;
@@ -141,7 +145,7 @@
* once the register value is not zero, the ramsize is
* this register's value multiply 64 * 1024 * 1024
*/
- for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
rambits = pci_read_config8(mc_dev, ramregs[i]);
if (rambits != 0)
@@ -150,17 +154,15 @@
/*
Get memory size and frame buffer from northbridge's registers.
if register with invalid value we set frame buffer size to 32M for default, but it won't happen.
-*/
+*/
reg = pci_read_config8(mc_dev, 0xa1);
reg &= 0x70;
reg = reg >> 4;
/* TOP 1M SM Memory */
- if (reg == 0x0)
- tomk = (((rambits << 6) - 32 - VIACONFIG_TOP_SM_SIZE_MB) * 1024); // Set frame buffer 32M for default
- else
- tomk =
- (((rambits << 6) - (4 << reg) -
- VIACONFIG_TOP_SM_SIZE_MB) * 1024);
+ if(reg == 0x0)
+ tomk = (((rambits << 6) - 32) * 1024); // Set frame buffer 32M for default
+ else
+ tomk = (((rambits << 6) - (4 << reg)) * 1024);
printk_spew("tomk is 0x%x\n", tomk);
/* Compute the Top Of Low Memory, in Kb */
@@ -172,24 +174,30 @@
/* Report the memory regions */
idx = 10;
/* TODO: Hole needed? */
- ram_resource(dev, idx++, 0, 640); /* first 640k */
+ ram_resource(dev, idx++, 0, 640); /* first 640k */
/* Leave a hole for vga, 0xa0000 - 0xc0000 */
ram_resource(dev, idx++, 768, (tolmk - 768));
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
}
assign_resources(&dev->link[0]);
}
static const struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = pci_domain_scan_bus,
-};
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = enable_childrens_resources,
+ .init = 0,
+ .scan_bus = pci_domain_scan_bus,
+};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(&dev->link[0]);
+ initialize_cpus(&dev->link[0]);
}
static void cpu_bus_noop(device_t dev)
@@ -197,27 +205,27 @@
}
static const struct device_operations cpu_bus_ops = {
- .read_resources = cpu_bus_noop,
- .set_resources = cpu_bus_noop,
- .enable_resources = cpu_bus_noop,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
printk_spew("In VX800 enable_dev for device %s.\n", dev_path(dev));
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
- dev->ops = &pci_domain_ops;
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ dev->ops = &pci_domain_ops;
pci_set_method(dev);
- } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
+ } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
struct chip_operations northbridge_via_vx800_ops = {
CHIP_NAME("VIA VX800 Chipset")
- .enable_dev = enable_dev,
+ .enable_dev = enable_dev,
};
===================================================================
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "chip.h"
+#include <arch/io.h>
+#include "vx800.h"
+#include "vx800_pci_io_modify_ops.h"
+
+void nb_host_bus_init(device_t dev)
+{
+ // fine-tune
+ // If no settings, C7 will hang or reboot in XP, but CN will not.
+ pci_modify_config8(dev, 0x51, 0x84, 0x00);
+ pci_modify_config8(dev, 0x52, 0x0F, 0x03);
+ pci_modify_config8(dev, 0x54, 0x04, 0x00);
+ pci_modify_config8(dev, 0x55, 0x04, 0x00);
+ pci_modify_config8(dev, 0x59, 0x09, 0x01);
+ pci_modify_config8(dev, 0x5C, 0x10, 0x10);
+ pci_modify_config8(dev, 0x5F, 0x0E, 0x08);
+ pci_modify_config8(dev, 0x92, 0xFF, 0x04); // ACPI Base addr
+ pci_modify_config8(dev, 0x97, 0x01, 0x01); // APIC MSI
+ pci_modify_config8(dev, 0x99, 0x02, 0x00); // APIC MSI
+ //GTL
+ pci_modify_config8(dev, 0x73, 0xFF, 0x66);
+ pci_modify_config8(dev, 0xB2, 0xFF, 0x33);
+ pci_modify_config8(dev, 0xB3, 0xFF, 0x33);
+ pci_modify_config8(dev, 0xBC, 0xFF, 0x33);
+ pci_modify_config8(dev, 0xBD, 0xFF, 0x33);
+ pci_modify_config8(dev, 0xC5, 0x30, 0x20);
+ pci_modify_config8(dev, 0xC8, 0x10, 0x00);
+}
+static struct device_operations nb_host_bus_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = nb_host_bus_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static struct pci_driver via_nb_host_bus_driver __pci_driver = {
+ .ops = &nb_host_bus_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX800_NB_HOST_BUS,
+};
===================================================================
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "chip.h"
+#include <arch/io.h>
+#include "vx800.h"
+#include "vx800_pci_io_modify_ops.h"
+
+void sb_vlink_init(device_t dev)
+{
+ pci_modify_config8(dev, 0xD1, 0x04, 0x00);// Setting HDAC enable
+
+ /*PCI1Init begin*/
+ //PCI1 Programming Sequence
+ //(1)Configure D17F7
+ pci_modify_config8(dev, 0x04, 0x00, 0x03);
+ pci_modify_config8(dev, 0x0C, 0x00, 0x08);
+ pci_modify_config8(dev, 0x4F, 0x40, 0x41); //RENPPB, RP2CFLSH
+ pci_modify_config8(dev, 0x77, 0x00, 0x48); //ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion
+ //pci_modify_config8(dev, 0x51, 0x00, 0x80); //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured.
+ //pci_modify_config8(dev, 0x51, 0x00, 0x81); //RSUB_DEC_P2P, RSUBDECOD(Window Vista)
+
+ //(2)Configure D19F0
+ device_t dev1;
+ dev1 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX800_SB_P2P, 0);
+ if(dev1)
+ pci_modify_config8(dev1, 0x04, 0x00, 0x07);
+
+ //(3)Performance Recommended Setting
+
+ //Save Power
+ pci_modify_config8(dev, 0xE2, 0x1F, 0x01);
+ pci_modify_config8(dev, 0xE3, 0xF1, 0x5E);
+ pci_modify_config8(dev, 0x74, 0x40, 0x00);
+ //Enhence Host To PCI cycle performance and PCI-To-Host Cycle performance
+ pci_modify_config8(dev, 0x70, 0x00, 0x82);
+ pci_modify_config8(dev, 0x71, 0x30, 0xC0);
+ pci_modify_config8(dev, 0x72, 0x00, 0xEE);
+
+ //Cycle Control
+ pci_modify_config8(dev, 0x73, 0x00, 0x01);
+ pci_modify_config8(dev, 0x74, 0x00, 0x0C);
+ //Arbitration control
+ pci_modify_config8(dev, 0x75, 0x00, 0x0F);
+ pci_modify_config8(dev, 0x76, 0x00, 0xD0);
+ /*PCI1Init end*/
+
+ /*CCAInit begin*/
+ pci_modify_config8(dev, 0xFC, 0x02, 0x48); //RVWREQ, ROABKDOOR
+ //CCA's Register Programming sequence
+ pci_modify_config8(dev, 0x50, 0x00, 0x08); //Config Azalia's upstream cycle high priority and other low priority
+ pci_modify_config8(dev, 0x51, 0x40, 0x80); //Disable bypass asynchronous circuit
+ pci_modify_config8(dev, 0x52, 0x00, 0x11); // Set SM Internal Device and HDAC Occupy Timer
+ pci_modify_config8(dev, 0x53, 0x00, 0x11); // Set SM Internal Device and HDAC Promote Timer
+ pci_modify_config8(dev, 0x54, 0xFF, 0x02); //Use SB internal devices's original REQ
+ pci_modify_config8(dev, 0x73, 0x10, 0x00); //RPINOWSC. Enable APIC Cycle Block P2C Write Cycle
+ pci_modify_config8(dev, 0x74, 0x00, 0x3C); //RLCKXP2C, RFSBVK.
+ pci_modify_config8(dev, 0xE1, 0x07, 0x00); //RBLKAPIC, RAZC3
+ pci_modify_config8(dev, 0x7C, 0x04, 0x02); //RNMIFSB, RFSBVK
+ pci_modify_config8(dev, 0xE0, 0xF0, 0x93); //RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme
+
+ pci_modify_config8(dev, 0xE7, 0xFF, 0x00); //Let CCA use dynamic clock.
+ //The CCA is also relate to D17F0
+ dev1 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX800_LPC, 0);
+ if(dev1)
+ //pci_modify_config8(dev1,0x49, 0x1F, 0x00); //Disable CCA Test Mode
+ pci_modify_config8(dev1, 0x74, 0xFF, 0x00); // Let DMA cycles from internal devices directly go to NB
+ /*CCAInit finish*/
+}
+
+void sb_vlink_enable(device_t dev)
+{
+ pci_modify_config8(dev, 0xE6, 0xFF, 0x39); // Enable SMM A-Seg, MSI and Io APIC
+
+ /*open hdac*/
+ pci_modify_config32(dev,0xd1,0x04,0);
+}
+static struct device_operations sb_vlink_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sb_vlink_init,
+ .enable = sb_vlink_enable,
+ .ops_pci = 0,
+};
+
+static struct pci_driver via_sb_vlink_driver __pci_driver = {
+ .ops = &sb_vlink_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX800_SB_VLINK,
+};
===================================================================
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "chip.h"
+#include <arch/io.h>
+#include "vx800.h"
+#include "vx800_pci_io_modify_ops.h"
+
+void ehci_init(device_t dev)
+{
+ pci_modify_config8(dev, 0x41, 0xFF, 0x20);
+ pci_modify_config8(dev, 0x42, 0xFF, 0x43);
+ pci_modify_config8(dev, 0x43, 0x00, 0xC0);
+ pci_modify_config8(dev, 0x48, 0x20, 0x9E);
+ pci_modify_config8(dev, 0x49, 0x10, 0x68);
+ pci_modify_config8(dev, 0x4B, 0xFF, 0x09);
+ pci_modify_config8(dev, 0x4C, 0xFF, 0x13);
+ pci_modify_config8(dev, 0x4D, 0x00, 0x94);
+ pci_modify_config8(dev, 0x4E, 0xFF, 0x03);
+ pci_modify_config8(dev, 0x4F, 0xFF, 0x10);
+ pci_modify_config8(dev, 0x50, 0x00, 0x80);
+ pci_modify_config8(dev, 0x52, 0xFF, 0x11);
+ pci_modify_config8(dev, 0x53, 0xFF, 0xbf);
+ pci_modify_config8(dev, 0x55, 0xFF, 0xff);
+ pci_modify_config8(dev, 0x56, 0xFF, 0x0f);
+ pci_modify_config8(dev, 0x5A, 0xFF, 0xCC);
+ pci_modify_config8(dev, 0x5B, 0xFF, 0xCC);
+ pci_modify_config8(dev, 0x5C, 0xFF, 0x00);
+ pci_modify_config8(dev, 0x5D, 0xFF, 0xCC);
+ pci_modify_config8(dev, 0x5E, 0x00, 0x00);
+ pci_modify_config8(dev, 0x64, 0xFF, 0x05);
+ //pci_modify_config8(dev, 0x6B, 0xFF, 0x01);
+ pci_modify_config8(dev, 0x6D, 0x00, 0x00);
+ pci_modify_config8(dev, 0x6F, 0xFF, 0x80);
+}
+
+static struct device_operations ehci_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = ehci_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static struct pci_driver via_ehci_driver __pci_driver = {
+ .ops = &ehci_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX800_EHCI,
+};
===================================================================
@@ -17,9 +17,21 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+uses CONFIG_WRITE_HIGH_TABLES
+
+default CONFIG_WRITE_HIGH_TABLES=1
+
config chip.h
-object vgabios.o
+object vx800_pci_io_modify_ops.o
driver northbridge.o
-driver vga.o
+#driver vga.o
driver vx800_lpc.o
driver vx800_ide.o
+driver vx800_nb_pmu.o
+driver vx800_nb_traf_ctrl.o
+driver vx800_nb_host_bus.o
+driver vx800_sb_vlink.o
+driver vx800_ehci.o
+driver vx800_nb_host_ctrl.o
+driver vx800_nb_pmu.o
+driver vx800_uhci.o
===================================================================
@@ -23,46 +23,46 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-
#include <pc80/mc146818rtc.h>
#include <pc80/keyboard.h>
#include <pc80/i8259.h>
#include "vx800.h"
#include "chip.h"
+#include "vx800_pci_io_modify_ops.h"
-static const unsigned char pciIrqs[4] = { 0xa, 0x9, 0xb, 0xa };
+static const unsigned char pciIrqs[4] = {0xa, 0x9, 0xb, 0xa};
-static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
+static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' };//only INTA
-static const unsigned char slotPins[4] = { 'A', 'A', 'A', 'A' }; //all 4
+static const unsigned char slotPins[4] = { 'A', 'A', 'A', 'A'};//all 4
-static const unsigned char usbdevicePins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
-static const unsigned char sdioPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
-static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
-static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' }; //only INTA
-static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
+static const unsigned char usbdevicePins[4] = { 'A', 'B', 'C', 'D' };//only INTA
+static const unsigned char sdioPins[4] = { 'A', 'B', 'C', 'D' };//only INTA
+static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' };//only INTA
+static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' };//only INTA
+static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' };//only INTA
-static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4
+static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' };//all 4
-static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
+static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' };//only INTA
static unsigned char *pin_to_irq(const unsigned char *pin)
{
static unsigned char Irqs[4];
int i;
- for (i = 0; i < 4; i++)
- Irqs[i] = pciIrqs[pin[i] - 'A'];
+ for (i = 0 ; i < 4 ; i++)
+ Irqs[i] = pciIrqs[ pin[i] - 'A' ];
return Irqs;
}
-static void pci_routing_fixup(struct device *dev)
+static void pci_routing_fixup(device_t dev)
{
printk_info("%s: dev is %p\n", __FUNCTION__, dev);
/* set up PCI IRQ routing */
pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
- pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4));
+ pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
/* VGA */
@@ -95,7 +95,7 @@
/* Standard usb components */
printk_info("setting usb1-2\n");
-// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
+ // pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
/* sound hardware */
printk_info("setting hdac audio\n");
@@ -104,34 +104,110 @@
printk_spew("%s: DONE\n", __FUNCTION__);
}
+#define R_SB_MULTI_FUNCTION_SELECT_1 0xE4
+#define R_SB_CX_STATE_BREAK_EVENT_ENABLE_1 0xE6
+#define PMIO_PROCESSOR_CONTROL 0x26
+#define R_SB_PCI_ARBITRATION_2 0x76
+#define R_SB_AUTO_SWITCH_P_STATE 0x8A
+
+void InitCPUCStatueSupport(device_t dev)
+{
+ u8 Mask, Value;
+
+ // Config Cx State
+ // Now it is C2 & C4 Up Down Mode
+ Mask = 0xFF;
+ Value = 0x30;
+ pci_modify_config8(dev, R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Mask, Value);//SB_LPC_REG
+
+ Mask = 0xFF;
+ Value = 0x1F;
+ io_modify_config8(VX800_ACPI_IO_BASE+PMIO_PROCESSOR_CONTROL, Mask, Value);
+
+ Mask = 0x00;
+ Value = 0x80;
+ device_t dev1;
+ dev1 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX800_SB_VLINK, 0);
+ if(dev1)
+ pci_modify_config8(dev1, R_SB_PCI_ARBITRATION_2, Mask, Value);//SB_VLINK_REG
+
+ Mask = 0xFF;
+ Value = 0x00;
+ pci_modify_config8(dev, R_SB_MULTI_FUNCTION_SELECT_1, Mask, Value);//SB_VLINK_REG
+
+ Mask = 0xFF;
+ Value = 0x1F;
+ pci_modify_config8(dev, R_SB_AUTO_SWITCH_P_STATE, Mask, Value);//SB_VLINK_REG
+}
+
+/// extern u8 acpi_slp_type; // FIXME
void setup_pm(device_t dev)
{
u16 tmp;
+
+ // Power Management
+ pci_modify_config8(dev, 0x80, 0x00, 0x20);
+ pci_modify_config8(dev, 0x8C, 0x02, 0x00);
+ pci_modify_config8(dev, 0x8D, 0x00, 0x18);
+
+ //Miscellaneous Configuration 1
+ pci_modify_config8(dev, 0x94, 0xF0, 0x28);
+ pci_modify_config8(dev, 0x95, 0x00, 0xC1);
+ pci_modify_config8(dev, 0x96, 0xFF, 0x10);
+ pci_modify_config8(dev, 0x97, 0x00, 0xB2);
+
+ //Voltage Change Function Enable
+ pci_modify_config8(dev, 0x9F, 0x00, 0x21);
+ //Internal PCIe and NM PLL Control
+ pci_modify_config8(dev, 0xE2, 0x00, 0xEA);
+
+ pci_modify_config8(dev, 0xE7, 0x00, 0x80);
+
+
+ u8 Mask, Value;
+ // Set SCI IRQ and its level trigger
+ Mask = 0x0F;
+ Value = 0x09;
+ pci_modify_config8(dev, 0x82, Mask, Value);
+
+ Mask = 0x02;
+ Value = 0x02;
+ io_modify_config8(0x4d1, Mask, Value);
+
+ // Enable ACPI
+ Mask = 0x01;
+ Value = 0x01;
+ io_modify_config8(VX800_ACPI_IO_BASE+0x04, Mask, Value);
+
+ InitCPUCStatueSupport(dev);
+
+
/* Debounce LID and PWRBTN# Inputs for 16ms. */
pci_write_config8(dev, 0x80, 0x20);
/* Set ACPI base address to IO VX800_ACPI_IO_BASE */
- pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 1);
+ pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE|1);
/* set ACPI irq to 9 */
pci_write_config8(dev, 0x82, 0x49);
/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
-// pci_write_config16(dev, 0x84, 0x30f2);
- pci_write_config16(dev, 0x84, 0x609a); // 0x609a??
+ // pci_write_config16(dev, 0x84, 0x30f2);
+ pci_write_config16(dev, 0x84, 0x609a); // 0x609a??
/* SMI output level to low, 7.5us throttle clock */
pci_write_config8(dev, 0x8d, 0x18);
/* GP Timer Control 1s */
pci_write_config8(dev, 0x93, 0x88);
-
+
/* Power Well */
pci_write_config8(dev, 0x94, 0x20); // 0x20??
/* 7 = stp to sust delay 1msec
- * 6 = SUSST# Deasserted Before PWRGD for STD
- */
+ * 6 = SUSST# Deasserted Before PWRGD for STD
+ */
pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
/* Disable GP2 & GP3 Timer */
@@ -156,6 +232,9 @@
outw(0xffff, VX800_ACPI_IO_BASE + 0x28);
outl(0xffffffff, VX800_ACPI_IO_BASE + 0x30);
+ // Enable Soft Resume
+ outw(inw(VX800_ACPI_IO_BASE+0x04)|0x8000, VX800_ACPI_IO_BASE+0x04);
+
/* Disable SCI on GPIO. */
outw(0x0, VX800_ACPI_IO_BASE + 0x22);
@@ -178,6 +257,7 @@
outb(0x0, VX800_ACPI_IO_BASE + 0x42);
tmp = inw(VX800_ACPI_IO_BASE + 0x04);
+ /// acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; // FIXME
/* SCI is generated for RTC/pwrBtn/slpBtn. */
tmp |= 1;
outw(tmp, VX800_ACPI_IO_BASE + 0x04);
@@ -198,52 +278,117 @@
*/
}
-void S3_ps2_kb_ms_wakeup(struct device *dev)
+void S3_ps2_kb_ms_wakeup(device_t dev)
{
u8 enables;
enables = pci_read_config8(dev, 0x51);
enables |= 2;
pci_write_config8(dev, 0x51, enables);
-
+
outb(0xe0, 0x2e);
- outb(0x0b, 0x2f); //if 09,then only support kb wakeup
+ outb(0x0b, 0x2f);//if 09,then only support kb wakeup
- outb(0xe1, 0x2e); //set any key scan code can wakeup
+ outb(0xe1, 0x2e);//set any key scan code can wakeup
outb(0x00, 0x2f);
-
- outb(0xe9, 0x2e); //set any mouse scan code can wakeup
+
+ outb(0xe9, 0x2e);//set any mouse scan code can wakeup
outb(0x00, 0x2f);
enables &= 0xd;
pci_write_config8(dev, 0x51, enables);
- outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02); //ACPI golabe enable for sci smi trigger
- outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME
+ outb(inb(VX800_ACPI_IO_BASE+0x02)|0x20, VX800_ACPI_IO_BASE+0x02);// ACPI golabe enable for sci smi trigger
+ outw(inw(VX800_ACPI_IO_BASE+0x22)|0x204, VX800_ACPI_IO_BASE+0x22);// ACPI SCI on Internal KBC and mouse PME
+}
+void S3_usb_wakeup(device_t dev)
+{
+ outw(inw(VX800_ACPI_IO_BASE+0x22)|0x4000, VX800_ACPI_IO_BASE+0x22);//SCI on USB PME
}
-void S3_usb_wakeup(struct device *dev)
+void S3_lid_wakeup(device_t dev)
{
- outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME
+ outw(inw(VX800_ACPI_IO_BASE+0x22)|0x800, VX800_ACPI_IO_BASE+0x22);//SCI on LID PME
}
-void S3_lid_wakeup(struct device *dev)
+#define HPET_ENABLE_BIT 0x80
+#define R_SB_HPET_CONTROL 0x68
+#define HPET_BASE_ADDRESS 0xFED0 // 0xFED00000
+#define R_SB_HPET_ADDRESS 0x69
+void HpetInit(device_t dev)
{
- outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME
+ pci_write_config8(dev, R_SB_HPET_CONTROL, HPET_ENABLE_BIT);
+ pci_write_config16(dev, R_SB_HPET_ADDRESS+1, HPET_BASE_ADDRESS);
}
+void WriteSbApicIndexedReg(u8 Idx, u32 Data)
+{
+ u32 Data32;
+ u32 ApicIdxAdr = VX800_APIC_SB_BASE;
+ u32 ApicDataAdr = VX800_APIC_SB_BASE + VX800_APIC_SB_DATA_OFFSET;
+ * ((u8 *)ApicIdxAdr)=Idx;
+ Data32=( * ((u32 *)ApicDataAdr));//this read is needed when write APIC ID ,dont know why.
+ Data32 = Data;
+ * ((u32 *)ApicDataAdr)=Data32;
+}
+
+void SbApicMmioRegInit(void)
+{
+ u32 Offset;
+ WriteSbApicIndexedReg(3, 1);
+ WriteSbApicIndexedReg(0, 4);
+ for(Offset = 0x10; Offset < VX800_APIC_SB_ENTRY_NUMBER; Offset += 2){
+ WriteSbApicIndexedReg(Offset + 1, 0);
+ WriteSbApicIndexedReg(Offset, 0x10000);
+ }
+}
+
+void vx800_ApicInit(device_t dev)
+{
+ device_t dev1;
+ pci_modify_config8(dev, 0x4D, 0x04, 0x00);
+ pci_modify_config8(dev, 0x5B, 0x0E, 0x00);
+ pci_modify_config8(dev, 0x6C, 0x08, 0x00);
+ pci_modify_config8(dev, 0x58, 0x00, 0x40);
+ dev1 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX800_SB_VLINK, 0);
+ if(dev1)
+ pci_modify_config8(dev1, 0x74, 0x00, 0x04);
+ //pci_modify_config8(dev1, 0x7C, 0x00, 0x7F);
+
+ SbApicMmioRegInit();
+}
+
/* This looks good enough to work, maybe */
-static void vx800_sb_init(struct device *dev)
+static void vx800_sb_init(device_t dev)
{
unsigned char enables;
+ /*BusControllerInit begin*/
+ pci_modify_config8(dev, 0x42, 0xF8, 0xF0); // ENLBUF, GINTREN, FLUSHEN, RBRSTRD
+ pci_modify_config8(dev, 0x43, 0x0F, 0x0B); // RENDTX, ENWBTO, ENRBTO
+ //pci_modify_config8(dev, 0x46, 0x00, 0x10); // It is related to INTH#
+ //pci_modify_config8(dev, 0x48, 0x00, 0x0C); //RMRPW, RIRPW
+ //pci_modify_config8(dev, 0x58, 0x00, 0x01); //RTC Rx32 Map to Centrury Byte//booting OS fail if set.
+ //pci_modify_config8(dev, 0x40, 0x00, 0x02); // RDMEGAS
+ pci_modify_config8(dev, 0x4C, 0xC0, 0x40);
+ pci_modify_config8(dev, 0x5B, 0x00, 0x51); // modify from 0x53 to 0x51
+ pci_modify_config8(dev, 0x67, 0x03, 0x01);
+
+ /*BusControllerInit end*/
+
+ HpetInit(dev);
+
+ vx800_ApicInit(dev);
+
+
// enable the internal I/O decode
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
// Map 4MB of FLASH into the address space
-// pci_write_config8(dev, 0x41, 0x7f);
+ // pci_write_config8(dev, 0x41, 0x7f);
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
@@ -261,7 +406,7 @@
pci_write_config8(dev, 0x4c, 0x44);
/* ROM memory cycles go to LPC. */
- pci_write_config8(dev, 0x59, 0x80);
+ pci_write_config8(dev, 0x59, 0x80);
/* Set 0x5b to 0x01 to match Award */
//pci_write_config8(dev, 0x5b, 0x01);
@@ -274,9 +419,9 @@
/* Set 0x58 to 0x42 APIC and RTC. */
//pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0.
- enables = pci_read_config8(dev, 0x58);
- enables |= 0x41; //
- pci_write_config8(dev, 0x58, enables);
+ enables=pci_read_config8(dev, 0x58);
+ enables|=0x40;//
+ pci_write_config8(dev, 0x58,enables);
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
enables = pci_read_config8(dev, 0x4f);
@@ -307,9 +452,9 @@
struct resource *resource;
pci_dev_read_resources(dev);
resource = new_resource(dev, 1);
- resource->flags |=
- IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO |
- IORESOURCE_STORED;
+ resource->flags |=
+ IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO |
+ IORESOURCE_STORED;
resource->size = 2;
resource->base = 0x2e;
@@ -318,13 +463,13 @@
void vx800_set_resources(device_t dev)
{
struct resource *resource;
- resource = find_resource(dev, 1);
+ resource = find_resource(dev,1);
resource->flags |= IORESOURCE_STORED;
pci_dev_set_resources(dev);
}
void vx800_enable_resources(device_t dev)
-{
+ {
/* vx800 is not a pci bridge and has no resources of its own (other than
standard PC i/o addresses). however it does control the isa bus and so
we need to manually call enable childrens resources on that bus */
@@ -333,21 +478,24 @@
enable_childrens_resources(dev);
}
-static void southbridge_init(struct device *dev)
-{
+
+
+static void lpc_init(device_t dev)
+{
printk_debug("vx800 sb init\n");
vx800_sb_init(dev);
pci_routing_fixup(dev);
- setup_i8259(); // make sure interupt controller is configured before keyboard init
+ setup_i8259(); // make sure interupt controller is configured before keyboard init
- /* turn on keyboard and RTC, no need to visit this reg twice */
+ /* turn on keyboard and RTC, no need to visit this reg twice */
init_pc_keyboard(0x60, 0x64, 0);
- printk_debug
- ("ps2 usb lid, you set who can wakeup system from s3 sleep\n");
- S3_ps2_kb_ms_wakeup(dev);
- S3_usb_wakeup(dev);
+ printk_debug("ps2 usb lid, you set who can wakeup system from s3 sleep\n");
+
+ S3_ps2_kb_ms_wakeup(dev);
+ S3_usb_wakeup(dev);
+
/* enable acpi cpu c3 state. (c2 state need not do anything.)
#1
fadt->pm2_cnt_blk = 0x22;//to support cpu-c3
@@ -355,7 +503,7 @@
fadt->p_lvl3_lat = 0x320;//
fadt->pm2_cnt_len = 1;//to support cpu-c3
#2
- ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
+ ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state")
#3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
1 enable SLP# asserts in C3 state PMIORx26<1> =1
2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1
@@ -368,20 +516,40 @@
PMIORx26<0> =0
6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15
*/
- outb(0x17, VX800_ACPI_IO_BASE + 0x26);
+ outb(0x17, VX800_ACPI_IO_BASE + 0x26);
}
+void lpc_enable(device_t dev)
+{
+ pci_modify_config8(dev, 0x41, 0x40, 0x40);
+
+ // Acpi init registers
+ pci_modify_config8(dev, 0x40, 0x44, 0x44); // Enable I/O Recovery Time, 4D0/4D1 Support
+ pci_modify_config8(dev, 0x4E, 0x00, 0x08);// Enable RTC port 74/75
+ pci_modify_config8(dev, 0x51, 0x0D, 0x0D);// and KBC
+ pci_modify_config8(dev, 0x52, 0x0F, 0x09); // Enable Serial IRQ
+ pci_modify_config8(dev, 0x67, 0x00, 0x04); // Set FERR voltage to 1.5v
+ pci_modify_config8(dev, 0x98, 0xFF, 0x00);// Disable GP3 Timer
+
+ ///// SPI-BAR.
+ //// SPI_BASE_ADDRESS = 0xFED1 0000
+ pci_modify_config8(dev, 0xBC, 0xFF, 0x00);
+ pci_modify_config8(dev, 0xBD, 0xFF, 0xD1);
+ pci_modify_config8(dev, 0xBE, 0xFF, 0xFE);
+}
+
static struct device_operations vx800_lpc_ops = {
- .read_resources = vx800_read_resources,
- .set_resources = vx800_set_resources,
+ .read_resources = vx800_read_resources,
+ .set_resources = vx800_set_resources,
.enable_resources = vx800_enable_resources,
- .init = &southbridge_init,
- .scan_bus = scan_static_bus,
+ .init = &lpc_init,
+ .scan_bus = scan_static_bus,
+ .enable =lpc_enable,
};
static struct pci_driver lpc_driver __pci_driver = {
- .ops = &vx800_lpc_ops,
+ .ops = &vx800_lpc_ops,
.vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_VX855_LPC,
+ .device = PCI_DEVICE_ID_VIA_VX800_LPC,
};
===================================================================
@@ -170,6 +170,7 @@
Tmp =
(u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) -
1) / ((DramAttr->DramCyc) << 2));
+ Tmp += 1;
PRINT_DEBUG_MEM("Trcd =");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
===================================================================
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "chip.h"
+#include <arch/io.h>
+#include "vx800.h"
+
+void nb_host_ctrl_enable(device_t dev)
+{
+ u32 subid=PCI_DEVICE_ID_VIA_VX800_NB_HOST_CTRL<<16+PCI_VENDOR_ID_VIA;
+ pci_write_config32(dev,0x2C,subid);
+}
+static struct device_operations nb_host_ctrl_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
+ .enable = nb_host_ctrl_enable,
+ .ops_pci = 0,
+};
+
+static struct pci_driver via_nb_host_ctrl_driver __pci_driver = {
+ .ops = &nb_host_ctrl_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX800_NB_HOST_CTRL,
+};
===================================================================
@@ -34,36 +34,6 @@
#define REV_B0 0x00
#define REV_B2 0x01
-/* VGA stuff */
-#define SR_INDEX 0x3c4
-#define SR_DATA 0x3c5
-#define CRTM_INDEX 0x3b4
-#define CRTM_DATA 0x3b5
-#define CRTC_INDEX 0x3d4
-#define CRTC_DATA 0x3d5
-
-/* Memory Controller Registers */
-#define RANK0_END 0x40
-#define RANK1_END 0x41
-#define RANK2_END 0x42
-#define RANK3_END 0x43
-#define RANK0_START 0x48
-#define RANK1_START 0x49
-#define RANK2_START 0x4a
-#define RANK3_START 0x4b
-#define DDR_PAGE_CTL 0x69
-#define DRAM_REFRESH_COUNTER 0x6a
-#define DRAM_MISC_CTL 0x6b
-#define CH_A_DQS_OUTPUT_DELAY 0x70
-#define CH_A_MD_OUTPUT_DELAY 0x71
-
-/* RAM Init Commands */
-#define RAM_COMMAND_NORMAL 0x0
-#define RAM_COMMAND_NOP 0x1
-#define RAM_COMMAND_PRECHARGE 0x2
-#define RAM_COMMAND_MRS 0x3
-#define RAM_COMMAND_CBR 0x4
-
/* IDE specific bits */
#define IDE_MODE_REG 0x09
#define IDE0_NATIVE_MODE (1 << 0)
@@ -85,8 +55,8 @@
#define VX800_ACPI_IO_BASE 0x0400
#define NB_APIC_REG 0,0,5,
-#define NB_PXPTRF_REG NB_APIC_REG
-#define NB_MSGC_REG NB_APIC_REG
+#define NB_PXPTRF_REG NB_APIC_REG
+#define NB_MSGC_REG NB_APIC_REG
#define NB_HOST_REG 0,0,2,
#define NB_P6IF_REG NB_HOST_REG
@@ -107,11 +77,12 @@
#define SB_USB2_REG 0,0x10, 2,
#define SB_EHCI_REG 0,0x10, 4,
-#define VX800SB_APIC_ID 0x4
-#define VX800SB_APIC_BASE 0xfec00000ULL
-#define VX800SB_APIC_DATA_OFFSET 0x10
-#define VX800SB_APIC_ENTRY_NUMBER 0x40
+#define VX800_APIC_SB_ID 0x4
+#define VX800_APIC_SB_BASE 0xfec00000ULL
+#define VX800_APIC_SB_DATA_OFFSET 0x10
+#define VX800_APIC_SB_ENTRY_NUMBER 0x40
+
#define VX800_D0F5_MMCONFIG_MBAR 0x61
#endif
===================================================================
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "chip.h"
+#include <arch/io.h>
+#include "vx800.h"
+#include "vx800_pci_io_modify_ops.h"
+void uhci_init(device_t dev)
+{
+ u8 Mask, Value;
+ u16 D16;
+ D16 = 0;
+ pci_write_config16(dev, 0x20, D16);
+
+ // Config some Control Register
+ Mask = 0x00;
+ Value = 0x12;
+
+ pci_modify_config8(dev, 0x41, Mask, Value);
+ Mask = 0x00;
+ Value = 0xEB;
+ pci_modify_config8(dev, 0x4B, Mask, Value);
+}
+
+static struct device_operations uhci_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = uhci_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static struct pci_driver via_uhci_driver __pci_driver = {
+ .ops = &uhci_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX800_UHCI,
+};
===================================================================
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef VX800_PCI_IO_MODIFY_OPS_FOR_AUTO_C
+#define VX800_PCI_IO_MODIFY_OPS_FOR_AUTO_C 1
+
+void pci_modify_config8(device_t dev, unsigned where,u8 mask,u8 orval)
+{
+ u8 data=pci_read_config8(dev,where);
+ data&=(~mask);
+ data|=orval;
+ pci_write_config8(dev,where,data);
+}
+void pci_modify_config16(device_t dev, unsigned where,uint16_t mask,uint16_t orval)
+{
+ uint16_t data=pci_read_config16(dev,where);
+ data&=(~mask);
+ data|=orval;
+ pci_write_config16(dev,where,data);
+}
+void pci_modify_config32(device_t dev, unsigned where, uint32_t mask,uint32_t orval)
+{
+ uint32_t data=pci_read_config32(dev,where);
+ data&=(~mask);
+ data|=orval;
+ pci_write_config32(dev,where,data);
+}
+void io_modify_config8(u16 where, uint8_t mask,uint8_t orval)
+{
+ u8 data=inb(where);
+ data&=(~mask);
+ data|=orval;
+ outb(data,where);
+}
+#endif
===================================================================
@@ -28,7 +28,7 @@
__romstrap_start:
tblpointer:
.long 0x55aa66cc
- .long 0x88012554
+ .long 0x88012454
.long 0x77107777
.long 0x00770814
===================================================================
@@ -180,7 +180,7 @@
pci_write_config8(MEMCTRL, 0xd5, Data);
Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xEF; /*clear bit7 */
+ Data &= 0x7F; /*clear bit7 */
if (DramAttr->RankNumChA > 2)
Data |= 0x80; /*if rank number > 2 (3or4), set bit7 */
else
@@ -370,7 +370,7 @@
else if (DIMMFREQ_667 == DramAttr->DramFreq)
FreqId = 2;
else if (DIMMFREQ_800 == DramAttr->DramFreq)
- FreqId = 4;
+ FreqId = 3;
else
FreqId = 0;
===================================================================
@@ -469,7 +469,7 @@
/* CL: really offset RX62[2:0] */
Data = pci_read_config8(MEMCTRL, 0x62);
- CL = Data & 0x03;
+ CL = Data & 0x07;
AccessAddr = (u32) (CHA_DDR2_MRS_table[CL]);
if (BL)
===================================================================
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "vx800.h"
+#include "vx800_pci_io_modify_ops.h"
+
+extern unsigned long log2(unsigned long x);
+
+static void mmconfig_set_resources(device_t dev)
+{
+ struct resource *resource;
+ u8 reg;
+
+ resource = find_resource(dev, VX800_D0F5_MMCONFIG_MBAR);
+ if (resource) {
+ report_resource_stored(dev, resource, "<mmconfig>");
+
+ /* Remember this resource has been stored. */
+ resource->flags |= IORESOURCE_STORED;
+ pci_write_config8(dev, VX800_D0F5_MMCONFIG_MBAR,
+ (resource->base >> 28));
+ reg = pci_read_config8(dev, 0x60);
+ reg |= 0x3;
+ /* Enable MMCONFIG decoding. */
+ pci_write_config8(dev, 0x60, reg);
+ }
+ pci_dev_set_resources(dev);
+}
+
+static void mmconfig_read_resources(device_t dev)
+{
+ struct resource *res;
+ pci_dev_read_resources(dev);
+
+ /* Add an MMCONFIG resource. */
+ res = new_resource(dev, VX800_D0F5_MMCONFIG_MBAR);
+ res->size = 256 * 1024 * 1024;
+ res->align = log2(res->size);
+ res->gran = log2(res->size);
+ res->limit = 0xffffffff; /* 4G */
+ res->flags = IORESOURCE_MEM;
+}
+
+void traf_ctrl_init(device_t dev)
+{
+ pci_modify_config8(dev, 0x50, 0x00, 0x00);
+ pci_modify_config8(dev, 0x54, 0x00, 0x80);
+ pci_modify_config8(dev, 0x55, 0x00, 0x04);
+ pci_modify_config8(dev, 0x58, 0x00, 0x00);
+ pci_modify_config8(dev, 0x59, 0x00, 0x02);
+ pci_modify_config8(dev, 0x5E, 0x00, 0x00);
+ pci_modify_config8(dev, 0x5F, 0x00, 0x06);
+ pci_modify_config8(dev, 0x80, 0x00, 0x18); //Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1.
+ pci_modify_config8(dev, 0x82, 0x00, 0x00); //Set RVC1RPSW, RVC1RQ1T to 1.
+ pci_modify_config8(dev, 0x83, 0x00, 0x81);
+ pci_modify_config8(dev, 0x84, 0x00, 0x28);
+ pci_modify_config8(dev, 0x85, 0x00, 0xC0);
+ pci_modify_config8(dev, 0xA3, 0x00, 0x01); // RWAKEEN,MSGC_REG
+ //pci_modify_config8(dev, 0x64, 0x40, 0x00); //RTDNP2B32EN
+ pci_modify_config8(dev, 0xF3, 0xFC, 0x20);
+ pci_modify_config8(dev, 0x85, 0x00, 0x00); //RP2P1ABORT
+}
+static const struct device_operations traf_ctrl_ops = {
+ .read_resources = mmconfig_read_resources,
+ .set_resources = mmconfig_set_resources,
+ .init = traf_ctrl_init,
+};
+
+/*NB APIC, PXPTRF and MSGC*/
+static const struct pci_driver traf_ctrl_driver __pci_driver = {
+ .ops = &traf_ctrl_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX800_NB_CTC,
+};
===================================================================
@@ -5,7 +5,7 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
+ * the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,69 +17,139 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-CB_STATUS DDR2_DRAM_INIT()
+#include <spd.h>
+#include <sdram_mode.h>
+#include <delay.h>
+
+#define DEBUG_RAM_SETUP 1
+
+#ifdef DEBUG_RAM_SETUP
+#define PRINT_DEBUG_MEM(x) print_debug(x)
+#define PRINT_DEBUG_MEM_HEX8(x) print_debug_hex8(x)
+#define PRINT_DEBUG_MEM_HEX16(x) print_debug_hex16(x)
+#define PRINT_DEBUG_MEM_HEX32(x) print_debug_hex32(x)
+#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
+#else
+#define PRINT_DEBUG_MEM(x)
+#define PRINT_DEBUG_MEM_HEX8(x)
+#define PRINT_DEBUG_MEM_HEX16(x)
+#define PRINT_DEBUG_MEM_HEX32(x)
+#define DUMPNORTH()
+#endif
+
+ #include "northbridge/via/vx800/translator_ddr2_init.c"
+ #include "northbridge/via/vx800/dram_init.h"
+ #include "northbridge/via/vx800/vx800_early_smbus.c"
+ #include "northbridge/via/vx800/dram_util.h"
+ #include "northbridge/via/vx800/dram_util.c"
+ #include "northbridge/via/vx800/detection.c"
+ #include "northbridge/via/vx800/freq_setting.c"
+ #include "northbridge/via/vx800/timing_setting.c"
+ #include "northbridge/via/vx800/drdy_bl.c"
+ #include "northbridge/via/vx800/driving_setting.c"
+ #include "northbridge/via/vx800/clk_ctrl.c"
+ #include "northbridge/via/vx800/dev_init.c"
+ #include "northbridge/via/vx800/rank_map.c"
+ #include "northbridge/via/vx800/dqs_search.c"
+ #include "northbridge/via/vx800/final_setting.c"
+ #include "northbridge/via/vx800/uma_ram_setting.c"
+
+/*
+ * Support one dimm with up to 2 ranks
+ */
+static void ddr2_ram_setup()
{
- CB_STATUS Status;
- u8 i;
+ u8 i, rambits, data;
+ u16 boot_mode;
u32 RamSize;
- BOOLEAN bTest;
DRAM_SYS_ATTR DramAttr;
PRINT_DEBUG_MEM("DRAM_INIT \r");
- memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
- /*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */
+ memset (&DramAttr, 0,sizeof (DRAM_SYS_ATTR));
+
+ /*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T*/
DRAMDetect(&DramAttr);
+
+ /* When resume from s3, draminit is skiped, so need to recovery any PCI register related to draminit.
+ and d0f3 didnt lost its Power during whole s3 time, so any register not belongs to d0f3 need to be recoveried . */
+ boot_mode = inw(VX800_ACPI_IO_BASE + 0x04);
+ boot_mode= ((boot_mode& (7 << 10)) >> 10) == 1 ? 3 : 0;
+ if (boot_mode==3) {
+ u8 ramregs[] = {0x43, 0x42, 0x41, 0x40};
+ device_t dev;
+ print_debug("This is a S3 wakeup\r\n");
+ /* begin to get ram size, 43,42 41 40 contains the end address of last rank in ddr2-slot */
+ dev=PCI_DEV(0, 0, 3);
+ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+ rambits = pci_read_config8(dev, ramregs[i]);
+ if (rambits != 0)
+ break;
+ }
- //Step2 set Frequency; calculate CL and Frequncy from SPD data; set the Frequency
- DRAMFreqSetting(&DramAttr);
- //Step3 Set DRAM Timing; CL, tRP, tRCD, tRAS, tRFC, tRRD, tWR, tWTR, tRTP
- DRAMTimingSetting(&DramAttr);
- //Step4 DRDY
- DRAMDRDYSetting(&DramAttr);
- //Step5 Burst length
- DRAMBurstLength(&DramAttr);
- //Step6 DRAM Driving Adjustment
- DRAMDriving(&DramAttr);
- //Step7 duty cycle control
- DutyCycleCtrl(&DramAttr);
- //Step8 DRAM clock phase and delay control
- DRAMClkCtrl(&DramAttr);
- //Step9 set register before init DRAM device
- DRAMRegInitValue(&DramAttr);
- //Step10 DDR and DDR2 initialize process
- DRAMInitializeProc(&DramAttr);
+ DRAMDRDYSetting (&DramAttr);
- //Step13 Interleave function in rankmap.c
- DRAMBankInterleave(&DramAttr);
- //Step14 Sizing
- DRAMSizingMATypeM(&DramAttr);
+ data = 0x80;//this value is same with DevInit.c
+ pci_write_config8(PCI_DEV(0,0,4), 0xa3, data);
+ pci_write_config8(PCI_DEV(0,17,7), 0x60, rambits<<2);
+ data=pci_read_config8(MEMCTRL, 0x88);
+ pci_write_config8(PCI_DEV(0,17,7), 0xE5, data);
- //Step11 Search DQS and DQ output delay
- DRAMDQSOutputSearch(&DramAttr);
- //Step12 Search DQS input delay
- DRAMDQSInputSearch(&DramAttr);
+ DRAMRegFinalValue(&DramAttr);
+ SetUMARam();
+ } else {
+ //Step2 set Frequency; calculate CL and Frequncy from SPD data; set the Frequency
+ DRAMFreqSetting(&DramAttr);
+ //Step3 Set DRAM Timing; CL, tRP, tRCD, tRAS, tRFC, tRRD, tWR, tWTR, tRTP
+ DRAMTimingSetting(&DramAttr);
+ //Step4 DRDY
+ DRAMDRDYSetting (&DramAttr);
+ //Step5 Burst length
+ DRAMBurstLength(&DramAttr);
+ //Step6 DRAM Driving Adjustment
+ DRAMDriving(&DramAttr);
+ //Step7 duty cycle control
+ DutyCycleCtrl(&DramAttr);
+ //Step8 DRAM clock phase and delay control
+ DRAMClkCtrl(&DramAttr);
+ //Step9 set register before init DRAM device
+ DRAMRegInitValue(&DramAttr);
+ //Step10 DDR and DDR2 initialize process
+ DRAMInitializeProc(&DramAttr);
+
+ //Step13 Interleave function in rankmap.c
+ DRAMBankInterleave(&DramAttr);
+ //Step14 Sizing
+ DRAMSizingMATypeM(&DramAttr);
- //Step15 DDR fresh counter setting
- DRAMRefreshCounter(&DramAttr);
- //Step16 Final register setting for improve performance
- DRAMRegFinalValue(&DramAttr);
+ //Step11 Search DQS and DQ output delay
+ DRAMDQSOutputSearch(&DramAttr);
+ //Step12 Search DQS input delay
+ DRAMDQSInputSearch(&DramAttr);
+
+ //Step15 DDR fresh counter setting
+ DRAMRefreshCounter(&DramAttr);
+ //Step16 Final register setting for improve performance
+ DRAMRegFinalValue(&DramAttr);
- RamSize = 0;
- for (i = 0; i < MAX_RANKS; i++) {
- if (DramAttr.RankSize[i] == 0) {
+ RamSize = 0;
+ for(i=0;i<MAX_RANKS;i++){
+ if (DramAttr.RankSize[i] == 0) {
continue;
+ }
+ RamSize += DramAttr.RankSize[i];
}
- RamSize += DramAttr.RankSize[i];
- }
- PRINT_DEBUG_MEM("RamSize=");
- PRINT_DEBUG_MEM_HEX32(RamSize);
- PRINT_DEBUG_MEM("\r");
- DumpRegisters(0, 3);
- //bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE);
- /* the memory can not correct work, this is because the user set the incorrect memory
- parameter from setup interface.so we must set the boot mode to recovery mode, let
- the system to reset and use the spd value to initialize the memory */
- SetUMARam();
- return CB_SUCCESS;
+ PRINT_DEBUG_MEM("RamSize=");
+ PRINT_DEBUG_MEM_HEX32(RamSize);
+ PRINT_DEBUG_MEM("\r");
+
+ ram_check(0, 640 * 1024);
+
+ /*BOOLEAN bTest;
+ bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE);*/
+ /* the memory can not correct work, this is because the user set the incorrect memory
+ parameter from setup interface.so we must set the boot mode to recovery mode, let
+ he system to reset and use the spd value to initialize the memory*/
+ SetUMARam();
+ }
}
===================================================================
@@ -20,6 +20,8 @@
#ifndef __DRAMINIT_H_
#define __DRAMINIT_H_
+#define MEMCTRL PCI_DEV(0,0,3)
+
//Dram Size
#define M (1024*1024)
#define M1 (1*M)
@@ -33,7 +35,7 @@
#define UMASIZE M64
#define ENABLE_CHC 0 //CHC enable, how ever, this CHC,used some reg define in CHB
-#define ENABLE_CHB 0 //CHB enable , CHB is VX800's, VX855 no this CHB.
+#define ENABLE_CHB 0 //CHB enable , CHB is VX800's, VX800 no this CHB.
//Dram Freq
#define DIMMFREQ_800 400
#define DIMMFREQ_667 333
@@ -108,11 +110,8 @@
#define SPD_SDRAM_TRFC 42 /*minimum refresh to active / refresh command period */
#define SPD_DATA_SIZE 44
-//Dram cofig are
-/*the most number of socket*/
-#define MAX_RAM_SLOTS 2
-#define MAX_SOCKETS MAX_RAM_SLOTS
+#define MAX_SOCKETS 2
#define MAX_DIMMS MAX_SOCKETS /*every sockets can plug one DIMM */
/*the most number of RANKs on a DIMM*/
#define MAX_RANKS MAX_SOCKETS*2
===================================================================
@@ -34,9 +34,10 @@
#include <cpu/x86/msr.h>
#include "chip.h"
#include "northbridge.h"
+
#include "vgachip.h"
-/* PCI Domain 1 Device 0 Function 0 */
+/* PCI Domain 0 Device 1 Function 0 */
#define SR_INDEX 0x3c4
#define SR_DATA 0x3c5
@@ -68,30 +69,37 @@
extern u8 acpi_sleep_type;
static void vga_init(device_t dev)
{
- uint8_t reg8;
-
print_debug("Initiailizing VGA...\n");
- u8 tmp8;
-//A20 OPEN
- tmp8 = inb(0x92);
- tmp8 = tmp8 | 2;
- outb(tmp8, 0x92);
+ pci_write_config8(dev, 0x3c, 0x0a);//same with vx800_lpc.c
+}
- //*
- //pci_write_config8(dev, 0x04, 0x07);
- //pci_write_config32(dev,0x10, 0xa0000008);
- //pci_write_config32(dev,0x14, 0xdd000000);
- pci_write_config32(dev, 0x10, VIACONFIG_VGA_PCI_10);
- pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14);
- pci_write_config8(dev, 0x3c, 0x0a); //same with vx855_lpc.c
- //*/
- printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+static void vx800_vga_enable_resources(device_t dev)
+{
+ device_t dev_use;
+ u8 data8, reg8;
+ u32 data32;
+ pci_dev_enable_resources(dev);
#if 1
- printk_debug("INSTALL REAL-MODE IDT\n");
- setup_realmode_idt();
- printk_debug("DO THE VGA BIOS\n");
+ /*1 enable direct cpu frame buffer access
+ 2 set D0F3RxA0A1[11:1] according to address in D1F0Rx10-13h, which was auto set by coreboot as a BAR.
+ */
+ data32=pci_read_config32(dev, 0x10)&0xfffffff0;
+ dev_use = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800_MEMCTRL, 0);
+ data8=pci_read_config8(dev_use, 0xa1);
+ data8 &=0xf0;
+ data8 |=(u8)(data32>>28);
+ pci_write_config8(dev_use, 0xa1, data8);
+ data8=(u8)(0xfe&(data32>>20));
+ data8=data8|0x01;
+ pci_write_config8(dev_use, 0xa0, data8);
+ //turn on GFx memory space access control for S.L(uma buffer in dram) and mmio
+ //THIS SHOULD BE SET AFTER umaseting and before VGABIOS called.
+ dev_use = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800_NB_HOST_CTRL, 0);
+ data8=pci_read_config8(dev_use, 0xD4);
+ data8 |= 0x03;
+ pci_write_config8(dev_use, 0xD4, data8);
do_vgabios();
if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {
printk_debug("Enable VGA console\n");
@@ -125,7 +133,7 @@
printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
}
-
+
static void vga_read_resources(device_t dev)
{
dev->rom_address = (void *)(0xffffffff - CONFIG_ROM_SIZE + 1);
@@ -134,15 +142,15 @@
}
static struct device_operations vga_operations = {
- .read_resources = vga_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = vga_init,
- .ops_pci = 0,
+ .read_resources = vga_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = vx800_vga_enable_resources,
+ .init = vga_init,
+ .ops_pci = 0,
};
static const struct pci_driver vga_driver __pci_driver = {
.ops = &vga_operations,
.vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_VX855_VGA,
+ .device = PCI_DEVICE_ID_VIA_VX800_VGA,
};
===================================================================
@@ -17,8 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include "pci_rawops.h"
-
typedef struct __UMA_RAM_tag {
u16 DramSize;
u8 D0F3Val;
@@ -50,9 +48,6 @@
#define VGA_PORT_32M 0xF0
#define VGA_PORT_16M 0xF8
-#define VIACONFIG_VGA_PCI_10 0xf8000008
-#define VIACONFIG_VGA_PCI_14 0xfc000000
-
static const UMARAM UMARamArr[] = {
{0, UMARAM_0M, FB_4M, 0xFE},
{8, UMARAM_8M, FB_8M, 0xFC},
@@ -64,17 +59,23 @@
{512, UMARAM_512M, FB_512M, VGA_PORT_512M},
{0xffff, 0xff, 0xff, 0xFF}
};
+static const u16 eae9_table[2][4] =
+ {
+ // FSB others
+ {250,350,350,350},
+ // FSB 800
+ {250,350,350,400}
+ };
void SetUMARam(void)
{
-#if 1
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
device_t vga_dev = PCI_DEV(0, 1, 0), d0f0_dev = PCI_DEV(0, 0, 0);
u8 ByteVal, temp;
UMARAM *pUMARamTable;
u16 UmaSize;
u8 SLD0F3Val, SLD1F0Val, VgaPortVal;
- u32 RamSize, SLBase, Tmp;
+ u32 RamSize, SLBase, Tmp,last_ram_rank_size;
u8 i;
PRINT_DEBUG_MEM("Entering vx800 SetUMARam.\n");
SLD0F3Val = 0;
@@ -117,12 +118,52 @@
//pci_write_config8(MEMCTRL, 0xb4, 0x04);
//enable CHA and CHB merge mode
- pci_write_config8(MEMCTRL, 0xde, 0x06);
+ ByteVal=pci_read_config8(MEMCTRL, 0xde);
+ ByteVal= ByteVal & 0xfd;
+ ByteVal= ByteVal | 0x04;
+ pci_write_config8(MEMCTRL, 0xde, ByteVal);
- //if can get the value from setup interface, so get the value
- //else use the default value
UmaSize = CONFIG_VIDEO_MB;
+ //check if CONFIG_VIDEO_MB> last_dram_rank_size, if so, have to degraded CONFIG_VIDEO_MB to last_dram_rank_size
+ for(RamSize = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+ RamSize = pci_read_config8(MEMCTRL, ramregs[i]);
+ if (RamSize != 0)
+ break;
+ }
+
+ if((RamSize<<6)==512){
+ ByteVal=pci_read_config8(d0f0_dev, 0xfe);
+ ByteVal|=0x80;
+ pci_write_config8(d0f0_dev, 0xfe,ByteVal);
+ }
+
+ last_ram_rank_size=RamSize-pci_read_config8(MEMCTRL, ramregs[i]+8);
+ last_ram_rank_size=last_ram_rank_size<<6;//M size.
+ if(UmaSize>last_ram_rank_size){
+ UmaSize=last_ram_rank_size;
+ print_emerg("!NOTICE\n");
+ print_emerg("!CONFIG_VIDEO_MB> last_dram_rank_size, have to set UmaSize=last_dram_rank_size=");
+ print_emerg_hex16(UmaSize);
+ print_emerg("");
+ print_emerg("M-HEX\n");
+ print_emerg("!END\n");
+ }
+ if((RamSize<<6)<=UmaSize){
+ UmaSize=UmaSize>>1;
+ print_emerg("!NOTICE\n");
+ print_emerg("!UmaSize> RamSize, have to set UmaSize= UmaSize/2=");
+ print_emerg_hex16(UmaSize);
+ print_emerg("M-HEX\n");
+ print_emerg("!END\n");
+ }
+
+ i=MAX_RANKS-i-1;
+ ByteVal=pci_read_config8(MEMCTRL, 0x95);
+ ByteVal&=0x55;
+ ByteVal|=0x02<<(i*2);
+ pci_write_config8(MEMCTRL, 0x95,ByteVal);
+
for (pUMARamTable = UMARamArr; pUMARamTable->DramSize != 0xffff;
pUMARamTable++) {
if (UmaSize == pUMARamTable->DramSize) {
@@ -137,7 +178,6 @@
ByteVal = (ByteVal & 0x8f) | (SLD0F3Val << 4);
pci_write_config8(MEMCTRL, 0xa1, ByteVal);
-// vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0);
//RxB2 may be for S.L. and RxB1 may be for L. L.
// It is different from Spec.
@@ -155,35 +195,6 @@
ByteVal = 0x07;
pci_write_config8(vga_dev, 0x04, ByteVal);
- //must set SL and MMIO base, or else when enable GFX memory space, system will hang
- //set S.L base
- Tmp = pci_read_config32(vga_dev, 0x10);
- Tmp = 0xfffffff8;
- pci_write_config32(vga_dev, 0x10, Tmp);
- Tmp = pci_read_config32(vga_dev, 0x10);
- Tmp = VIACONFIG_VGA_PCI_10;
- pci_write_config32(vga_dev, 0x10, Tmp);
-
- //set MMIO base
- Tmp = pci_read_config32(vga_dev, 0x14);
- Tmp = 0xfffffffC;
- pci_write_config32(vga_dev, 0x14, Tmp);
- Tmp = pci_read_config32(vga_dev, 0x14);
- Tmp = VIACONFIG_VGA_PCI_14;
- pci_write_config32(vga_dev, 0x14, Tmp);
-
-//enable direct cpu frame buffer access
- i = pci_rawread_config8(PCI_RAWDEV(0, 0, 3), 0xa1);
- i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28);
- pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa1, i);
- pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa0, 0x01);
-
- //enable GFx memory space access control for S.L and mmio
- ByteVal = pci_read_config8(d0f0_dev, 0xD4);
- ByteVal |= 0x03;
- //ByteVal |= 0x01;
- pci_write_config8(d0f0_dev, 0xD4, ByteVal);
-
//enable Base VGA 16 Bits Decode
ByteVal = pci_read_config8(d0f0_dev, 0xfe);
ByteVal |= 0x10;
@@ -203,28 +214,25 @@
//ByteVal = 0x03;
//pci_write_config8(d0f0_dev, 0xc0, ByteVal);
- //Turn on Graphic chip IO port port access
+ //Enable access of graphic io port
ByteVal = inb(0x03C3);
ByteVal |= 0x01;
outb(ByteVal, 0x03C3);
- //Turn off Graphic chip Register protection
+ //Disable protect graphic chip register
outb(0x10, 0x03C4);
ByteVal = inb(0x03C5);
ByteVal |= 0x01;
outb(ByteVal, 0x03C5);
- //set VGA memory Frequence
+ //set VGA memory frequence
//direct IO port 0x3DX to vga io space 0x3C2[0]
ByteVal = inb(0x03CC);
ByteVal |= 0x03;
outb(ByteVal, 0x03C2);
- // ByteVal=inb(0x03C2);
- // ByteVal |= 0x01;
- // outb(ByteVal,0x03C2);
-#if 1 //bios porting guide has no this two defination: 3d on 3d4/3d5 and 39 on 3c4/3c5
+ //bios porting guide has no this two defination: 3d on 3d4/3d5 and 39 on 3c4/3c5
//set frequence 0x3D5.3d[7:4]
outb(0x3d, 0x03d4);
@@ -260,8 +268,7 @@
outb(0x39, 0x03c4);
outb(1 << SLD0F3Val, 0x03c5);
-#endif
- // Set S.L. size in GFX's register
+ // Set S.L. size
outb(0x68, 0x03c4);
outb(VgaPortVal, 0x03c5);
@@ -333,99 +340,32 @@
ByteVal = (ByteVal & 0xE5) | 0x1A;
outb(ByteVal, 0x03d5);
- u8 table3c43c5[0x70] = {
- 0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x78, 0x00, 0x00, 0x00, 0xBE, 0x20, 0x7F,
- 0x60, 0x7F, 0x08, 0x31, 0xCC, 0x00, 0x01, 0x00,
- 0x00, 0x18, 0x10, 0x00, 0x00, 0x00, 0x3D, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x04, 0xF3, 0xFF, 0xFC,
- 0xF8, 0x0C, 0x00, 0x00, 0x40, 0x06, 0x11, 0x22,
- 0x51, 0x10, 0x00, 0x01, 0x19, 0x0C, 0x00, 0xFF,
- 0x38, 0x40, 0x30, 0xFF, 0x70, 0x8C, 0x85, 0x9D,
- 0x80, 0x05, 0x54, 0x90, 0x03, 0x30, 0x00, 0x5F,
- 0x1F, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00,
- 0x06, 0xDF, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x40, 0x20, 0x00, 0x20, 0x20,
- 0xE0, 0x20, 0xD0, 0x3F, 0x00, 0xE0, 0x00, 0x00
- };
- u8 table3d43d5[0x88] = {
- 0x7F, 0x63, 0x63, 0x83, 0x69, 0x19, 0x72, 0xE0,
- 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x58, 0x9C, 0x57, 0x90, 0x00, 0x57, 0x73, 0xE3,
- 0x57, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x0C, 0x00, 0x11, 0x06, 0x00, 0x20, 0x01, 0x34,
- 0xEE, 0x74, 0x01, 0x01, 0x08, 0x84, 0x00, 0x00,
- 0x00, 0xF3, 0x40, 0x90, 0x00, 0x00, 0x00, 0x01,
- 0x00, 0x12, 0x00, 0x02, 0x00, 0x00, 0x10, 0x00,
- 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D,
- 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x9D,
- 0x9D, 0x9D, 0x9D, 0x9D, 0x00, 0x9D, 0x1D, 0x00,
- 0x00, 0x00, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
- 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
- };
+ ByteVal=pci_read_config8(MEMCTRL, 0xa7);
+ ByteVal |= 0x0c;
+ pci_write_config8(MEMCTRL, 0xa7,ByteVal);
- u8 table3c0space[0xc0] = {
- 0x11, 0x00, 0x10, 0x01, 0x26, 0x3D, 0xFF, 0x00,
- 0x10, 0x3F, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x50, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- };
-#if 0
-//for(i=0;i<0xc0;i++)
- for (i = 0; i < 0x40; i++) //
- {
- outb(table3c0space[i], 0x03c0 + i);
- }
+ ByteVal = 0xee;
+ pci_write_config8(MEMCTRL, 0xa2,ByteVal);
- for (i = 0; i < 0x70; i++) {
- outb(i, 0x03c4);
- outb(table3c43c5[i], 0x03c5);
+ ByteVal=pci_read_config8(MEMCTRL, 0xc0);
+ ByteVal |= 0x01;
+ pci_write_config8(MEMCTRL, 0xc0,ByteVal);
+
+ u8 freq;
+ u16 D0F4RxEAE9;
+ ByteVal=pci_read_config8(PCI_DEV(0,0,2), 0x54);
+ freq=pci_read_config8(MEMCTRL, 0x90);
+ freq&=0x07;
+ freq=freq-3;
+ if((ByteVal&0xE0)!=0x60){
+ D0F4RxEAE9=eae9_table[0][freq];
+ }else{
+ D0F4RxEAE9=eae9_table[1][freq];
}
- for (i = 0; i < 0x88; i++) {
- outb(i, 0x03d4);
- outb(table3d43d5[i], 0x03d5);
- }
- outb(0x92, 0x03d4);
- outb(0x80, 0x03d5);
+ pci_write_config8(PCI_DEV(0,0,4), 0xe9,(u8)(D0F4RxEAE9));
+ pci_write_config8(PCI_DEV(0,0,4), 0xea,(u8)(D0F4RxEAE9>>8));
- outb(0xa3, 0x03d4);
- outb(0x00, 0x03d5);
-
- outb(0xe8, 0x03d4);
- outb(0x40, 0x03d5);
-#endif
-//3d4 3d freq
-//IO Port / Index: 3X5.3D
-//Scratch Pad Register 4
-
-// outb(0x39,0x03c4);//
- //outb(1 << SLD0F3Val ,0x03c5);
-//
-#endif
-
-}
+ ByteVal=pci_read_config8(PCI_DEV(0,17,0), 0x9b);
+ ByteVal|=0x80;
+ pci_write_config8(PCI_DEV(0,17,0), 0x9b,ByteVal);
+}
\ No newline at end of file
===================================================================
@@ -15,93 +15,125 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-
-/*
- * Enable the serial devices on the VIA
*/
-#include <arch/romcc_io.h>
+
+#define USE_VCP 0//0 means use DVP
+#define USE_COM1 1
+#define USE_COM2 0
-/* The base address is 0x15c, 0x2e, depending on config bytes */
+#define gCom1Base 0x3f8
+#define gCom2Base 0x2f8
+void EmbedComInit()
+{
+ u8 ByteVal;
+ u16 ComBase;
-#define SIO_BASE 0x3f0
-#define SIO_DATA SIO_BASE+1
+ //enable NB multiple function control
+ ByteVal = pci_read_config8(PCI_DEV(0, 0, 0), 0x4f);
+ ByteVal = ByteVal |0x01;
+ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal);
+ //Enable VGA
+ ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA1);
+ ByteVal = ByteVal |0x80;
+ pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal);
+ ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA7);
+ ByteVal = ByteVal |0x08;
+ pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal);
+ //Enable p2p IO/ and mem
+ ByteVal = pci_read_config8(PCI_DEV(0, 1, 0), 0x4);
+ ByteVal = ByteVal |0x07;
+ pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal);
+ //Enable Graphic chip IO port port access
+ ByteVal = inb(0x3C3);
+ ByteVal = ByteVal |0x01;
+ outb(ByteVal,0x3C3);
+ //Disable Graphic chip Register protection
+ outb(0x10,0x3C4);
+ ByteVal = inb(0x3C5);
+ ByteVal = ByteVal |0x01;
+ outb(ByteVal,0x3C5);
-static void vx800_writesuper(uint8_t reg, uint8_t val)
-{
- outb(reg, SIO_BASE);
- outb(val, SIO_DATA);
-}
+ //enable south module pad share
+ outb(0x78,0x3C4);
+ ByteVal = inb(0x3C5);
+ ByteVal = ByteVal |0x80;
+ outb(ByteVal,0x3C5);
-static void vx800_writepnpaddr(uint8_t val)
-{
- outb(val, 0x2e);
- outb(val, 0xeb);
-}
+ //enable UART Function multiplex with DVP or VCP pad D17F0Rx46[7,6]
+ ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0x46);
+ //multiplex with VCP
+ if(USE_VCP == 1)
+ ByteVal = (ByteVal & 0x3F) | 0x40;
+ //multiplex with DVP
+ else
+ ByteVal = (ByteVal & 0x3F) | 0xC0;
+ pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal);
-static void vx800_writepnpdata(uint8_t val)
-{
- outb(val, 0x2f);
- outb(val, 0xeb);
-}
+ //enable embeded com1 and com2 D17F0RxB0[5,4]
+ ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0);
+ ByteVal = ByteVal & 0xcf;
+ //multiplex with VCP
+ if(USE_COM1==1)
+ ByteVal = ByteVal | 0x10;
+ if(USE_COM2==1)
+ ByteVal = ByteVal | 0x20;
+ pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal);
-static void vx800_writesiobyte(uint16_t reg, uint8_t val)
-{
- outb(val, reg);
-}
+ if(USE_COM1 == 1)
+ ComBase = gCom1Base;
+ else
+ ComBase = gCom2Base;
-static void vx800_writesioword(uint16_t reg, uint16_t val)
-{
- outw(val, reg);
-}
-/* regs we use: 85, and the southbridge devfn is defined by the
- mainboard
- */
+ //noharddrive
+ //set embeded com1 IO base = 0x3E8
+ //D17F0RB4
+ //ByteVal = 0xFD;
+ if(USE_COM1==1){
+ ByteVal = (u8)((gCom1Base >> 3) |0x80);
+ pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal);
+ ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2);
+ ByteVal = (ByteVal&0xf0)|0x04;
+ pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal);
+ }
+ //set embeded com2 IO base = 0x2E8
+ //D17F0RB5
+ //ByteVal = 0xDD;
+ if(USE_COM2==1){
+ ByteVal = (u8)((gCom2Base >> 3) |0x80);
+ pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal);
+ ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2);
+ ByteVal = (ByteVal&0x0f)|0x30;
+ pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal);
+ }
-static void enable_vx800_serial(void)
-{
- outb(6, 0x80);
- outb(0x03, 0x22);
- //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e);
- //pci_write_config8(PCI_DEV(0,17,0),0xb0,0x10);
+ //disable interrupt
+ inb(ComBase + 3);
+ outb(ByteVal & 0x7F,ComBase + 3);
+ outb( 0x00,ComBase + 1);
- // turn on pnp
- vx800_writepnpaddr(0x87);
- vx800_writepnpaddr(0x87);
- // now go ahead and set up com1.
- // set address
- vx800_writepnpaddr(0x7);
- vx800_writepnpdata(0x2);
- // enable serial out
- vx800_writepnpaddr(0x30);
- vx800_writepnpdata(0x1);
- // serial port 1 base address (FEh)
- vx800_writepnpaddr(0x60);
- vx800_writepnpdata(0xfe);
- // serial port 1 IRQ (04h)
- vx800_writepnpaddr(0x70);
- vx800_writepnpdata(0x4);
- // serial port 1 control
- vx800_writepnpaddr(0xf0);
- vx800_writepnpdata(0x2);
- // turn of pnp
- vx800_writepnpaddr(0xaa);
+ //set baudrate
+ ByteVal = inb(ComBase + 3);
+ outb( ByteVal | 0x80,ComBase + 3);
+ outb(0x01,ComBase);
+ outb(0x00,ComBase + 1 );
- // set up reg to set baud rate.
- vx800_writesiobyte(0x3fb, 0x80);
- // Set 115 kb
- vx800_writesioword(0x3f8, 1);
- // Set 9.6 kb
- // WRITESIOWORD(0x3f8, 12)
- // now set no parity, one stop, 8 bits
- vx800_writesiobyte(0x3fb, 3);
- // now turn on RTS, DRT
- vx800_writesiobyte(0x3fc, 3);
- // Enable interrupts
- vx800_writesiobyte(0x3f9, 0xf);
- // should be done. Dump a char for fun.
- vx800_writesiobyte(0x3f8, 48);
- outb(7, 0x80);
+ //set frame fromat
+ ByteVal = inb(ComBase + 3);
+ outb( ByteVal & 0x3F,ComBase + 3);
+ outb(0x03,ComBase + 3 );
+ outb(0x00,ComBase + 2);
+ outb(0x00,ComBase + 4);
+
+ /*send a 'A' to test the function of COM*/
+ //outb(0x41,ComBase);
}
+
+static void enable_vx800_serial(void)
+{
+ EmbedComInit();
+
+ /*enable COM at 2E8-2EF(COM4) and 3E8-3EF(COM3),external COM port (if it is ON your MB)*/
+ pci_write_config8(PCI_DEV(0, 17, 0), 0x6e, 0xdf);
+}
\ No newline at end of file
===================================================================
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "chip.h"
+#include <arch/io.h>
+#include "vx800.h"
+#include "vx800_pci_io_modify_ops.h"
+void nb_pmu_init(device_t dev)
+{
+ pci_modify_config8(dev, 0x84, 0x00, 0xDB);
+ pci_modify_config8(dev, 0x85, 0x00, 0x05);
+ pci_modify_config8(dev, 0x89, 0x00, 0xF8);
+ pci_modify_config8(dev, 0x8B, 0x00, 0xBF);
+ pci_modify_config8(dev, 0x8D, 0x00, 0xFC);
+ pci_modify_config8(dev, 0x8E, 0x00, 0x19);
+ pci_modify_config8(dev, 0x8F, 0x03, 0x00);
+ pci_modify_config8(dev, 0x90, 0x00, 0xFF);
+ pci_modify_config8(dev, 0x91, 0x00, 0xFF);
+ pci_modify_config8(dev, 0x92, 0x00, 0xCC);
+ pci_modify_config8(dev, 0xA0, 0x00, 0x80);
+ pci_modify_config8(dev, 0xA1, 0x00, 0xE0);
+ pci_modify_config8(dev, 0xA2, 0x00, 0xD6);
+ pci_modify_config8(dev, 0xA3, 0x00, 0x80);
+ pci_modify_config8(dev, 0xA8, 0x00, 0x20);
+}
+
+static struct device_operations nb_pmu_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = nb_pmu_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static struct pci_driver via_nb_pmu_driver __pci_driver = {
+ .ops = &nb_pmu_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX800_NB_PMU,
+};
===================================================================
@@ -81,7 +81,6 @@
{0x60, 0xff, 0xD0},
{0x66, 0xcf, 0x80}, // DRAMC queue > 2
{0x69, 0xff, 0x07}, // Enable multiple page
- {0x95, 0x00, 0x0D},
{0x96, 0x0F, 0xA0},
{0xFB, 0x00, 0x3E},
{0xFD, 0x00, 0xA9},
@@ -112,12 +111,26 @@
//enable dram By-Rank self refresh
Data = pci_read_config8(MEMCTRL, 0x96);
Data &= 0xF0;
- for (i = 0x01; i < 0x10; i = i << 1) {
+ for (i = 0x01; i < (1<<MAX_RANKS); i = i << 1) {
if ((DramAttr->RankPresentMap & i) != 0x00)
Data |= i;
}
pci_write_config8(MEMCTRL, 0x96, Data);
+ u8 shift = 1;
+ Data=0;
+ for (i = 0; i < MAX_RANKS; i++){
+ if ((DramAttr->RankPresentMap & shift) != 0){
+ Data|=1<<(i*2);
+ }
+ shift <<= 1;
+ }
+ pci_write_config8(MEMCTRL, 0x95,Data);
+
+ Data=pci_read_config8(MEMCTRL, 0xde);
+ Data |= 0x04;
+ pci_write_config8(MEMCTRL, 0xde,Data);
+
for (i = 0; i < PM_table_item; i++) {
Data = pci_read_config8(PCI_DEV(0, 0, 4), PM_table[i][0]);
Data = (u8) ((Data & PM_table[i][1]) | PM_table[i][2]);
===================================================================
@@ -204,7 +204,7 @@
/* call vga bios int 10 function 0x4f14 to enable main console
epia-m does not always autosence the main console so forcing it on is good !! */
-void vga_enable_console()
+void vga_enable_console(void)
{
if ((acpi_sleep_type == 0)/* && (PAYLOAD_IS_SEABIOS == 1)*/)
return;
===================================================================
@@ -203,7 +203,7 @@
dev =
pci_locate_device(PCI_ID
- (PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC),
+ (PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800_LPC),
0);
if (dev == PCI_DEV_INVALID) {
===================================================================
@@ -26,6 +26,8 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <device/pci.h>
+#include <arch/io.h>
+#include <pc80/mc146818rtc.h>
u8 acpi_checksum(u8 *table, u32 length)
{
@@ -563,6 +565,12 @@
{
/* just restore the SMP trampoline and continue with wakeup on assembly level */
memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
- acpi_jmp_to_realm_wakeup((u32) vector);
+ //acpi_jmp_to_realm_wakeup((u32) vector);
+
+ /*Seabios at entry_post:(in romlayout.S) will check cmos[0x0f] as a S3 resuming flag.
+ Seabios sets bit 7 in order to disable the NMI - it shouldn't hurt to always set bit 7*/
+ outb(0x8f, RTC_BASE_PORT + 0);
+ outb(0xfe, RTC_BASE_PORT + 1);
+ acpi_jmp_to_realm_wakeup(0xffff0);
}
#endif
===================================================================
@@ -0,0 +1,48 @@
+##
+## This file is part of the coreboot project.
+##
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target via_vx800example
+mainboard via/vx800example
+
+option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=10
+option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=10
+
+
+#define framebuffer size of VX800's integrated graphics card. support 32 64 128 256 512.
+#CONFIG_VIDEO_MB can only be used in uma_ram_setting.c, should not be referenced in other file!
+#Since:
+#CONFIG_VIDEO_MB should not > last DDR2 rank size...
+#if unfortunately, CONFIG_VIDEO_MB>last_rank_size, then in UMARamSetting.c
+#the umasize(CONFIG_VIDEO_MB) will be automatically degraded to =last_ram_rank_size.
+option CONFIG_VIDEO_MB =512
+
+
+#
+# Generate the final ROM like this:
+# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
+# 65536=size of vgabios I used
+
+option CONFIG_ROM_SIZE = 512* 1024
+
+romimage "fallback"
+ option COREBOOT_EXTRA_VERSION = "-VIA MB vx800example"
+ payload ../payload.elf
+end
+
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
This is an updated version of the VX800 patch from http://www.coreboot.org/pipermail/coreboot/2009-July/050785.html It contains the following changes to make it build (vx800example board): - Add CONFIG_ prefix to lots of variables (I may have missed some). - Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP (which is in bytes not KB now). - Fix acpi_write_rsdp() call (not enough parameters). - ram/ramtest.c moved to lib/ramtest.c. - Renames a la s/HAVE_ACPI_TABLES/CONFIG_GENERATE_ACPI_TABLES/ etc. - Disable ACPI table stuff for now, doesn't build yet. - Disable CONFIG_HAVE_ACPI_RESUME for now. - Disable CONFIG_GENERATE_ACPI_TABLES for now. - Drop no longer available variables: - CONFIG_MAX_PCI_BUSES - CONFIG_CBFS - CONFIG_ROM_PAYLOAD_START - PAYLOAD_SIZE - Disable vga.o in Config.lb for now, doesn't build. - Comment out acpi_slp_type usage for now, won't build otherwise. - Drop Config-abuild.lb, it's not needed (abuild works fine). IMPORTANT: This patch should not be merged as is (yet), it will definately break the VIA EPIA-M700 target and also has lots of whitespace breakage in it which I want to remove first (will post updated patch). Uwe.