Add initial support for the HP e-Vectra P2706T.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
===================================================================
@@ -3,6 +3,7 @@
depends on VENDOR_HP
source "src/mainboard/hp/dl145_g3/Kconfig"
+source "src/mainboard/hp/e_vectra_p2706t/Kconfig"
endchoice
===================================================================
@@ -0,0 +1,60 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# FIXME: It's a PC87360 actually.
+# FIXME: It's an i810E actually!
+# FIXME: ROM chip size really 512KB?
+config BOARD_HP_E_VECTRA_P2706T
+ bool "e-Vectra P2706T"
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_PGA370
+ select NORTHBRIDGE_INTEL_I82810
+ select SOUTHBRIDGE_INTEL_I82801XX
+ select SUPERIO_NSC_PC87360
+ select HAVE_PIRQ_TABLE
+ select UDELAY_TSC
+ select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+ select BOARD_ROMSIZE_KB_512
+
+config MAINBOARD_DIR
+ string
+ default hp/e_vectra_p2706t
+ depends on BOARD_HP_E_VECTRA_P2706T
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "e-Vectra P2706T"
+ depends on BOARD_HP_E_VECTRA_P2706T
+
+config HAVE_OPTION_TABLE
+ bool
+ default n
+ depends on BOARD_HP_E_VECTRA_P2706T
+
+config IRQ_SLOT_COUNT
+ int
+ default 3
+ depends on BOARD_HP_E_VECTRA_P2706T
+
+config VIDEO_MB
+ int
+ default 1
+ depends on BOARD_HP_E_VECTRA_P2706T
+
===================================================================
@@ -0,0 +1,131 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
+
+arch i386 end
+driver mainboard.o
+if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
+makerule ./failover.E
+ depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+ depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+ # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+ action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+ action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if CONFIG_USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if CONFIG_USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu_enable.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx_disable.inc
+dir /pc80
+config chip.h
+
+# TODO: i810E actually!
+chip northbridge/intel/i82810 # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on
+ device pci 0.0 on end # Host bridge
+ chip drivers/pci/onboard # Onboard VGA
+ device pci 1.0 on end
+ register "rom_address" = "0xfff80000" # 512 KB image
+ end
+ chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA/LPC bridge
+ # TODO: PC87364 actually!
+ # TODO: Check Super I/O settings and compare to superiotool -d.
+ chip superio/nsc/pc87360 # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end # SWC
+ device pnp 2e.5 off end # PS/2 mouse
+ device pnp 2e.6 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.8 off end # ACB
+ device pnp 2e.9 off end # FSCM
+ device pnp 2e.a off end # WDT
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.2 on end # USB
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 on end # AC'97 audio
+ device pci 1f.6 off end # AC'97 modem (N/A ?)
+ end
+ end
+end
+
===================================================================
@@ -0,0 +1,62 @@
+# TODO: i810E actually!
+chip northbridge/intel/i82810 # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on
+ device pci 0.0 on end # Host bridge
+ chip drivers/pci/onboard # Onboard VGA
+ device pci 1.0 on end
+ register "rom_address" = "0xfff80000" # 512 KB image
+ end
+ chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA/LPC bridge
+ # TODO: PC87364 actually!
+ # TODO: Check Super I/O settings and compare to superiotool -d.
+ chip superio/nsc/pc87360 # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end # SWC
+ device pnp 2e.5 off end # PS/2 mouse
+ device pnp 2e.6 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.8 off end # ACB
+ device pnp 2e.9 off end # FSCM
+ device pnp 2e.a off end # WDT
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.2 on end # USB
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 on end # AC'97 audio
+ device pci 1f.6 off end # AC'97 modem (N/A ?)
+ end
+ end
+end
+
===================================================================
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+include $(src)/mainboard/Makefile.romccboard.inc
+
===================================================================
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x1f << 3) | 0x0, /* Interrupt router device */
+ 0x0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x2410, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x59, /* Checksum */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0},
+ {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
+ {0x00, (0x1f << 3) | 0x0, {{0xfe, 0x4000}, {0x61, 0xdeb8}, {0x00, 0x0000}, {0x63, 0xdeb8}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
===================================================================
@@ -0,0 +1,99 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+uses CONFIG_GENERATE_MP_TABLE
+uses CONFIG_GENERATE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses COREBOOT_EXTRA_VERSION
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_GENERATE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_WRITE_HIGH_TABLES
+uses CONFIG_VIDEO_MB
+
+default CONFIG_ROM_SIZE = 512 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_GENERATE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
+default CONFIG_GENERATE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 3
+default CONFIG_MAINBOARD_VENDOR = "HP"
+default CONFIG_MAINBOARD_PART_NUMBER = "e-Vectra P2706T"
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
+default CONFIG_ROM_PAYLOAD = 1
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default HOSTCC = "gcc"
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3 # 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+default CONFIG_CONSOLE_VGA = 1
+default CONFIG_PCI_ROM_RUN = 1
+default CONFIG_WRITE_HIGH_TABLES = 1
+default CONFIG_VIDEO_MB = 1
+end
===================================================================
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+};
===================================================================
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "lib/ramtest.c"
+/* TODO: It's a PC87364 actually! */
+#include "superio/nsc/pc87360/pc87360_early_serial.c"
+/* TODO: It's i810E actually! */
+#include "northbridge/intel/i82810/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+#include "pc80/udelay_io.c"
+#include "lib/debug.c"
+#include "northbridge/intel/i82810/raminit.c"
+
+/* TODO: It's a PC87364 actually! */
+#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
+
+static void main(unsigned long bist)
+{
+ if (bist == 0)
+ early_mtrr_init();
+
+ /* TODO: It's a PC87364 actually! */
+ pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ uart_init();
+ console_init();
+
+ enable_smbus();
+
+ report_bist_failure(bist);
+
+ /* dump_spd_registers(); */
+ sdram_set_registers();
+ sdram_set_spd_registers();
+ sdram_enable();
+ /* ram_check(0, 640 * 1024); */
+}
===================================================================
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("HP e-Vectra P2706T Mainboard")
+};
===================================================================
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target e_vectra_p2706t
+mainboard hp/e_vectra_p2706t
+
+option CONFIG_ROM_SIZE = 512 * 1024
+
+romimage "normal"
+ option CONFIG_USE_FALLBACK_IMAGE = 0
+ option COREBOOT_EXTRA_VERSION = ".0Normal"
+ payload ../payload.elf
+end
+
+romimage "fallback"
+ option CONFIG_USE_FALLBACK_IMAGE = 1
+ option COREBOOT_EXTRA_VERSION = ".0Fallback"
+ payload ../payload.elf
+end
+
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
+