Patchwork SPI support for intel i82580

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Submitter Michael Stickel
Date 2016-03-23 10:04:29
Message ID <2063173694.59220.1458727469025.JavaMail.zimbra@mycable.de>
Download mbox | patch
Permalink /patch/4431/
State New
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Comments

Michael Stickel - 2016-03-23 10:04:29
Hi Stefan,

> > we have a added and tested support for the intel i82580 to the nicintel_spi driver.
> > Is anyone else working on that topic or should I post the patch. This could conflict with the i350 patch http://patchwork.coreboot.org/patch/4394/.
> > Should our patch be based on a clear 0.9.9 release or on a 0.9.9 + i350 patch.
>
> we have no idea if the i350 patch really works and we won't merge it
> till someone has tested it. Thus your approach of basing it on the last
> commit (i.e. on the 0.9.9 release) is just fine. The conflicts can't be
> too bad anyway since the i350 patch is not large at all. Thanks in
> advance for the patch!

find the patch attached. You will see, that it's impact is as small as with the i350 patch. It's just the id's and the offset to the flash registers.

I have introduced a small helper function called nicintel_spi_get_flash_register_offset. The purpose is to make the code more readable and to move the offset more closely to the definition of the pci-devices.


We have found out some things that might be interesting for others. Is there a place where such things can be put, e.g. a wiki?
- with an unprogrammed eeprom the i82580 detects the eeprom as 16KB, even if the eeprom is 32KB.
- if the eeprom of flash is not programmed (has device-id 1509), the igb driver does not recognize the card and does not enable it. The device must be enable via sysfs prior to programming (e.g. echo 1 > /sys/bus/pci/devices/0000:01:00.0/enable). Only one device needs to be programmed, as they all share the same eeprom.

Any comments to the patch are welcome.

best regards
Michael

Patch

--- flashrom-0.9.9-orig/nicintel_spi.c	2014-12-05 22:56:13.000000000 +0000
+++ flashrom-0.9.9/nicintel_spi.c	2016-03-22 10:10:15.973468573 +0000
@@ -95,9 +95,40 @@ 
 	{PCI_VENDOR_ID_INTEL, 0x152a, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller with FCoE"},
 	{PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit SFI Network Controller"},
 
+#define UNPROG_DEVICE 0x1509
+        {PCI_VENDOR_ID_INTEL, 0x150e, NT, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"},
+        {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"},
+        {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"},
+        {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"},
+        {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"},
+        {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, NT, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"},
+
 	{0},
 };
 
+static int nicintel_spi_get_flash_register_offset(struct pci_dev * dev)
+{
+	switch(dev->device_id)
+	{
+	case 0x10d8:
+	case 0x10f7:
+	case 0x10f8:
+	case 0x10f9:
+	case 0x10fb:
+	case 0x10fc:
+	case 0x1517:
+	case 0x151c:
+	case 0x1529:
+	case 0x152a:
+	case 0x1557:
+		return 0x10000;
+	default:
+		break;
+	}
+	return 0;
+}
+
+
 static void nicintel_request_spibus(void)
 {
 	uint32_t tmp;
@@ -198,13 +229,9 @@ 
 	if (!io_base_addr)
 		return 1;
 
-	if (dev->device_id < 0x10d8) {
-		nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr,
+	const int flash_register_offset = nicintel_spi_get_flash_register_offset(dev);
+	nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + flash_register_offset,
 					   MEMMAP_SIZE);
-	} else {
-		nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000,
-					   MEMMAP_SIZE);
-	}
 	if (nicintel_spibar == ERROR_PTR)
 		return 1;