| Submitter | Myles Watson |
|---|---|
| Date | 2009-10-20 18:21:52 |
| Message ID | <2831fecf0910201121i2d3b40ccj30b602c478584bfe@mail.gmail.com> |
| Download | mbox | patch |
| Permalink | /patch/445/ |
| State | Superseded |
| Headers | show |
Comments
On Tue, Oct 20, 2009 at 12:21 PM, Myles Watson <mylesgw@gmail.com> wrote: > > > On Tue, Oct 20, 2009 at 11:45 AM, Hugh Greenberg <hng@lanl.gov> wrote: > >> Myles, >> >> Here is the full output after flashing the latest revision and the patch: >> > Thanks. The IDs that got printed looked fine. How about disabling SMP > (patch attached) after updating to the latest? > By the way, I still haven't seen the "ht_reset" I'd expect from a cold boot in your logs. At least until we figure something out, could you make sure to power cycle each time? Thanks, Myles
On Tue, Oct 20, 2009 at 12:59 PM, Myles Watson <mylesgw@gmail.com> wrote: > > > On Tue, Oct 20, 2009 at 12:21 PM, Myles Watson <mylesgw@gmail.com> wrote: >> >> >> On Tue, Oct 20, 2009 at 11:45 AM, Hugh Greenberg <hng@lanl.gov> wrote: >>> >>> Myles, >>> >>> Here is the full output after flashing the latest revision and the patch: >> >> Thanks. The IDs that got printed looked fine. How about disabling SMP >> (patch attached) after updating to the latest? > > By the way, I still haven't seen the "ht_reset" I'd expect from a cold boot > in your logs. At least until we figure something out, could you make sure > to power cycle each time? > I was wondering if it is getting stuck in the chipset reset code. The last message seems to be that it is ignoring the other AP and going to do the reset. Marc
I have been power cycling since you pointed it out last time.
On Tue, Oct 20, 2009 at 1:31 PM, Hugh Greenberg <hng@lanl.gov> wrote:
> I have been power cycling since you pointed it out last time.
So have you been editing the logs (removing the first bit before the HT
reset)?
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
This is link 0, and it says it is already running at the maximum frequency,
so it doesn't need a reset. A cold boot should start at 200MHz and always
need a reset. Here's an example from SimNOW:
dev1 old_freq=0x0, freq=0x4, needs_reset=0x1
dev2 old_freq=0x0, freq=0x4, needs_reset=0x1
If you haven't been editing the logs, then maybe there's something wrong
with the early serial port initialization. That would be good to know.
Thanks,
Myles
No, I haven't been editing the logs. I sent you exactly what I saw on the serial port.
On Tue, Oct 20, 2009 at 1:50 PM, Hugh Greenberg <hng@lanl.gov> wrote: > No, I haven't been editing the logs. I sent you exactly what I saw on the > serial port. > Good to know. I didn't think you would, but there's a big chunk missing. Thanks, Myles
Oops. I did miss a big chunk of the log :). I thought it was part of the previous output. Here is the full log: coreboot-2.3 Tue Oct 20 11:36:27 MDT 2009 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done SBLink=00 NC node|link=00 enterinlg ahpti_co patpiimci zied_ li0n1k pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x0, freq=0x4, needs_reset=0x1 dev2 old_freq=0x0, freq=0x4, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 ht reset - coreboot-2.3 Tue Oct 20 11:36:27 MDT 2009 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done SBLink=00 NC node|link=00 iapicen taepriicn gi d ht_0o1p mize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram2.01 Enabling dual channel memory Registered 166Mhz RAM end at 0x00200000 kB Lower RAM end at 0x00200000 kB Ram3
On Tue, Oct 20, 2009 at 2:01 PM, Hugh Greenberg <hng@lanl.gov> wrote: > Oops. I did miss a big chunk of the log :). I thought it was part of the > previous output. Here is the full log: OK. That looks better. Now did you try applying no_smp.diff? Thanks, Myles
Yes. Here is the output: coreboot-2.3 Tue Oct 20 14:42:33 MDT 2009 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x0, freq=0x4, needs_reset=0x1 dev2 old_freq=0x0, freq=0x4, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 ht reset - coreboot-2.3 Tue Oct 20 14:42:33 MDT 2009 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram3
Patch
Index: src/mainboard/arima/hdama/Kconfig =================================================================== --- src/mainboard/arima/hdama/Kconfig (revision 4819) +++ src/mainboard/arima/hdama/Kconfig (working copy) @@ -58,12 +58,12 @@ config MAX_CPUS int - default 4 + default 1 depends on BOARD_ARIMA_HDAMA config MAX_PHYSICAL_CPUS int - default 2 + default 1 depends on BOARD_ARIMA_HDAMA config HW_MEM_HOLE_SIZE_AUTO_INC