Patchwork [Fwd:,Re:,[Fwd:,Re:,arima,hdama,problem] ]

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Submitter Myles Watson
Date 2009-10-20 21:44:30
Message ID <2831fecf0910201444q4e3431a5rdaa41234c5420b6d@mail.gmail.com>
Download mbox | patch
Permalink /patch/448/
State Superseded
Headers show

Comments

Myles Watson - 2009-10-20 21:44:30
On Tue, Oct 20, 2009 at 3:27 PM, Hugh Greenberg <hng@lanl.gov> wrote:

> Ram3
> Before starting clocks: Before memreset:
>
It looks like it's dying in udelay.  I don't know why, but I put in a
timeout to see if that helps us get past it.

Thanks,
Myles
Hugh Greenberg - 2009-10-20 21:58:36
Seems to have gotten farther:

coreboot-2.3 Tue Oct 20 15:51:22 MDT 2009 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
started ap apicid:
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x0, freq=0x4, needs_reset=0x1
dev2 old_freq=0x0, freq=0x4, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
ht reset -


coreboot-2.3 Tue Oct 20 15:51:22 MDT 2009 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
started ap apicid:
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
setting up CPU01 northbridge registers
done.
Ram2.00
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00100000 kB
Lower RAM end at 0x00100000 kB
Ram2.01
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00200000 kB
Lower RAM end at 0x00200000 kB
Ram3
Before starting clocks: Before memreset: cpu is pre_c0
after first udelay
after second udelay
Before controllers loop: ECC enabled
ECC enabled
Before 2nd controllers loop: Initializing memory:  done
Initializing memory:  done
Before hole: Ram4
v_esp=000ced88
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Jumping to image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: load fallback/coreboot_ram @ 1048576/409600 bytes, enter @ 100000
Stage: done loading.
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-2.3 Tue Oct 20 15:51:22 MDT 2009 booting...
POST: 0x40
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:18.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:00.2: enabled 0, 0 resources
PCI: 00:01.0: enabled 0, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 0, 2 resources
PNP: 002e.2: enabled 0, 2 resources
PNP: 002e.3: enabled 1, 2 resources
PNP: 002e.4: enabled 0, 0 resources
PNP: 002e.5: enabled 0, 0 resources
PNP: 002e.6: enabled 1, 3 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 0, 0 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 0, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:01.2: enabled 1, 0 resources
PCI: 00:01.3: enabled 1, 0 resources
I2C: 00:70: enabled 1, 0 resources
I2C: 00:2c: enabled 1, 0 resources
I2C: 00:50: enabled 1, 0 resources
I2C: 00:51: enabled 1, 0 resources
I2C: 00:52: enabled 1, 0 resources
I2C: 00:53: enabled 1, 0 resources
I2C: 00:54: enabled 1, 0 resources
I2C: 00:55: enabled 1, 0 resources
I2C: 00:56: enabled 1, 0 resources
I2C: 00:57: enabled 1, 0 resources
PCI: 00:01.5: enabled 0, 0 resources
PCI: 00:01.6: enabled 1, 0 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 0 resources
PCI: 00:19.0: enabled 1, 0 resources
PCI: 00:19.1: enabled 1, 0 resources
PCI: 00:19.2: enabled 1, 0 resources
PCI: 00:19.3: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:18.0: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
   PCI: 00:00.1: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
   PCI: 00:01.1: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
    PCI: 00:00.0: enabled 1, 0 resources
    PCI: 00:00.1: enabled 1, 0 resources
    PCI: 00:00.2: enabled 0, 0 resources
    PCI: 00:01.0: enabled 0, 0 resources
    PCI: 00:06.0: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
    PNP: 002e.0: enabled 0, 3 resources
    PNP: 002e.1: enabled 0, 2 resources
    PNP: 002e.2: enabled 0, 2 resources
    PNP: 002e.3: enabled 1, 2 resources
    PNP: 002e.4: enabled 0, 0 resources
    PNP: 002e.5: enabled 0, 0 resources
    PNP: 002e.6: enabled 1, 3 resources
    PNP: 002e.7: enabled 0, 0 resources
    PNP: 002e.8: enabled 0, 0 resources
    PNP: 002e.9: enabled 0, 0 resources
    PNP: 002e.a: enabled 0, 0 resources
   PCI: 00:01.1: enabled 1, 0 resources
   PCI: 00:01.2: enabled 1, 0 resources
   PCI: 00:01.3: enabled 1, 0 resources
    I2C: 00:70: enabled 1, 0 resources
     I2C: 00:2c: enabled 1, 0 resources
    I2C: 00:50: enabled 1, 0 resources
    I2C: 00:51: enabled 1, 0 resources
    I2C: 00:52: enabled 1, 0 resources
    I2C: 00:53: enabled 1, 0 resources
    I2C: 00:54: enabled 1, 0 resources
    I2C: 00:55: enabled 1, 0 resources
    I2C: 00:56: enabled 1, 0 resources
    I2C: 00:57: enabled 1, 0 resources
   PCI: 00:01.5: enabled 0, 0 resources
   PCI: 00:01.6: enabled 1, 0 resources
  PCI: 00:18.1: enabled 1, 0 resources
  PCI: 00:18.2: enabled 1, 0 resources
  PCI: 00:18.3: enabled 1, 0 resources
  PCI: 00:19.0: enabled 1, 0 resources
  PCI: 00:19.1: enabled 1, 0 resources
  PCI: 00:19.2: enabled 1, 0 resources
  PCI: 00:19.3: enabled 1, 0 resources
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  PCI: 00:18.3 siblings=0
CPU: APIC: 00 enabled
  PCI: 00:19.3 siblings=0
malloc Enter, size 1100, free_mem_ptr 00160000
malloc 00160000
CPU: APIC: 01 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:18.0 [1022/1100] bus ops
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:18.4, bad id 0xffffffff
PCI: 00:18.5, bad id 0xffffffff
PCI: 00:18.6, bad id 0xffffffff
PCI: 00:18.7, bad id 0xffffffff
PCI: 00:19.0 [1022/1100] bus ops
PCI: 00:19.0 [1022/1100] enabled
PCI: 00:19.1 [1022/1101] enabled
PCI: 00:19.2 [1022/1102] enabled
PCI: 00:19.3 [1022/1103] ops
PCI: 00:19.3 [1022/1103] enabled
PCI: 00:19.4, bad id 0xffffffff
PCI: 00:19.5, bad id 0xffffffff
PCI: 00:19.6, bad id 0xffffffff
PCI: 00:19.7, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0, bad id 0xffffffff
PCI: 00:1e.0, bad id 0xffffffff
PCI: 00:1f.0, bad id 0xffffffff
POST: 0x25

Patch

Index: svn/src/lib/generic_sdram.c
===================================================================
--- svn.orig/src/lib/generic_sdram.c
+++ svn/src/lib/generic_sdram.c
@@ -58,6 +58,7 @@  void sdram_initialize(int controllers, c
 	print_debug("Ram3\r\n");
 
 	#if RAMINIT_SYSINFO == 1
+	#error "RAMINIT_SYSINFO set "
 	sdram_enable(controllers, ctrl, sysinfo);
 	#else
 	sdram_enable(controllers, ctrl);
Index: svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/arima/hdama/cache_as_ram_auto.c
+++ svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
@@ -56,10 +56,13 @@  static void memreset_setup(void)
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 	if (is_cpu_pre_c0()) {
+               	print_info("cpu is pre_c0 \r\n");
 		udelay(800);
+               	print_info("after first udelay \r\n");
 		/* Set memreset_high */
 		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
 		udelay(90);
+               	print_info("after second udelay \r\n");
 	}
 }
 
@@ -157,33 +160,22 @@  void cache_as_ram_main(unsigned long bis
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const struct mem_controller cpu[] = {
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
+	static const uint16_t spd_addr [] = {
+		(0xa<<3)|0, (0xa<<3)|2, 0, 0,
+		(0xa<<3)|1, (0xa<<3)|3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
+		(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+		(0xa<<3)|5, (0xa<<3)|7, 0, 0,
 #endif
 	};
 
         int needs_reset;
+	unsigned bsp_apicid = 0;
+	struct mem_controller ctrl[8];
+	unsigned nodes;
 
         if (bist == 0) {
-		init_cpus(cpu_init_detectedx);
+		bsp_apicid = init_cpus(cpu_init_detectedx);
         }
 
 	pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -200,6 +192,7 @@  void real_main(unsigned long bist, unsig
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
         start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
 #endif
         // automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
@@ -209,11 +202,17 @@  void real_main(unsigned long bist, unsig
                	soft_reset();
        	}
 
+	allow_all_aps_stop(bsp_apicid);
+
+	nodes = get_nodes();
+
+	fill_mem_ctrl(nodes, ctrl, spd_addr);
+
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
-	post_cache_as_ram();
+	sdram_initialize(nodes, ctrl);
 
+	post_cache_as_ram();
 }
Index: svn/src/northbridge/amd/amdk8/raminit.c
===================================================================
--- svn.orig/src/northbridge/amd/amdk8/raminit.c
+++ svn/src/northbridge/amd/amdk8/raminit.c
@@ -2237,6 +2237,7 @@  static void sdram_enable(int controllers
 		die("No memory\n");
 	}
 
+	printk_debug("Before starting clocks: ");
 	/* Before enabling memory start the memory clocks */
 	for (i = 0; i < controllers; i++) {
 		uint32_t dch;
@@ -2256,10 +2257,12 @@  static void sdram_enable(int controllers
 		}
 	}
 
+	printk_debug("Before memreset: ");
 	/* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
 	/* And if necessary toggle the the reset on the dimms by hand */
 	memreset(controllers, ctrl);
 
+	printk_debug("Before controllers loop: ");
 	for (i = 0; i < controllers; i++) {
 		uint32_t dcl, dch;
 		if (!controller_present(ctrl + i))
@@ -2292,6 +2295,7 @@  static void sdram_enable(int controllers
 		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 	}
 
+	printk_debug("Before 2nd controllers loop: ");
 	for (i = 0; i < controllers; i++) {
 		uint32_t dcl, dch;
 		if (!controller_present(ctrl + i))
@@ -2328,6 +2332,7 @@  static void sdram_enable(int controllers
 		printk_debug(" done\n");
 	}
 
+	printk_debug("Before hole: ");
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 	 // init hw mem hole here
 	/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
Index: svn/src/cpu/amd/model_fxx/apic_timer.c
===================================================================
--- svn.orig/src/cpu/amd/model_fxx/apic_timer.c
+++ svn/src/cpu/amd/model_fxx/apic_timer.c
@@ -19,11 +19,13 @@  void init_timer(void)
 void udelay(unsigned usecs)
 {
 	uint32_t start, value, ticks;
+	uint32_t timeout=0;
 	/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
 	ticks = usecs * 200;
 	start = lapic_read(LAPIC_TMCCT);
 	do {
 		value = lapic_read(LAPIC_TMCCT);
-	} while((start - value) < ticks);
+		timeout++;
+	} while(((start - value) < ticks) && (timeout < 1000000));
 	
 }