| Submitter | Libra Li |
|---|---|
| Date | 2009-10-21 04:02:23 |
| Message ID | <df21912a0910202102r10906ab0l38f67aede239c251@mail.gmail.com> |
| Download | mbox | patch |
| Permalink | /patch/450/ |
| State | Accepted |
| Commit | r4822 |
| Headers | show |
Comments
Hello, Thanks for the patch! Libra Li wrote: > --- src/mainboard/technexion/tim5690/mainboard.c (revision 4821) .. > - > -/*************************************************** > -* This board, the TIM-5690 has two Marvel 88e5056 PCI-E > -* 10/100/1000 chips on board. > -* Both of their pin PERSTn pins are connected to GPIO 5 of the > -* SB600 southbridge. > -****************************************************/ > -static void enable_onboard_nic() > -{ Can you explain briefly why this code can be removed without loss of functionality? Is it simply not needed for this board? Thanks! //Peter
Hi, Peter,
The LAN chip-set enabled by hardware. So it need not activable by
software.
Thanks.
2009/10/21 Peter Stuge <peter@stuge.se>
> Hello, Thanks for the patch!
>
> Libra Li wrote:
> > --- src/mainboard/technexion/tim5690/mainboard.c (revision 4821)
> ..
> > -
> > -/***************************************************
> > -* This board, the TIM-5690 has two Marvel 88e5056 PCI-E
> > -* 10/100/1000 chips on board.
> > -* Both of their pin PERSTn pins are connected to GPIO 5 of the
> > -* SB600 southbridge.
> > -****************************************************/
> > -static void enable_onboard_nic()
> > -{
>
> Can you explain briefly why this code can be removed without loss of
> functionality?
>
> Is it simply not needed for this board?
>
>
> Thanks!
>
> //Peter
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
On 21.10.2009 06:02, Libra Li wrote: > Hi, > > This is little modification for TIM-5690. > Thanks. > > Signed-off-by: Libra Li <libra.li@technexion.com> > Thanks for the patch. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> and committed in r4822. Regards, Carl-Daniel
Patch
Index: src/mainboard/technexion/tim5690/mainboard.c =================================================================== --- src/mainboard/technexion/tim5690/mainboard.c (revision 4821) +++ src/mainboard/technexion/tim5690/mainboard.c (working copy) @@ -47,37 +47,6 @@ uint64_t uma_memory_base, uma_memory_size; - -/*************************************************** -* This board, the TIM-5690 has two Marvel 88e5056 PCI-E -* 10/100/1000 chips on board. -* Both of their pin PERSTn pins are connected to GPIO 5 of the -* SB600 southbridge. -****************************************************/ -static void enable_onboard_nic() -{ - - u8 byte; - device_t sm_dev; - - printk_info("enable_onboard_nic.\n"); - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0x9a); - byte |= ( 1 << 7); - pci_write_config8(sm_dev, 0x9a, byte); - - byte=pm_ioread(0x59); - byte &= ~( 1<< 5); - pm_iowrite(0x59,byte); - - byte = pci_read_config8(sm_dev, 0xA8); - - byte |= (1 << 1); //set bit 1 to high - pci_write_config8(sm_dev, 0xA8, byte); -} - /* set thermal config */ static void set_thermal_config() @@ -193,7 +162,6 @@ uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif - enable_onboard_nic(); set_thermal_config(); } Index: targets/technexion/tim5690/Config.lb =================================================================== --- targets/technexion/tim5690/Config.lb (revision 4821) +++ targets/technexion/tim5690/Config.lb (working copy) @@ -8,9 +8,6 @@ #option CONFIG_ROM_SIZE = (1024*1024*2) #option CONFIG_ROM_SIZE = (1024*1024*4) -option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 - - romimage "normal" option CONFIG_USE_FALLBACK_IMAGE=0 option CONFIG_ROM_IMAGE_SIZE=0x20000
Hi, This is little modification for TIM-5690. Thanks. Signed-off-by: Libra Li <libra.li@technexion.com>