Patchwork [Fwd:,Re:,[Fwd:,Re:,[Fwd:,Re:,arima,hdama,problem] ]]

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Submitter Myles Watson
Date 2009-10-21 20:31:55
Message ID <2831fecf0910211331y3f9b9265r23d7021db1d1a4f4@mail.gmail.com>
Download mbox | patch
Permalink /patch/456/
State Superseded
Headers show

Comments

Myles Watson - 2009-10-21 20:31:55
On Wed, Oct 21, 2009 at 2:21 PM, Hugh Greenberg <hng@lanl.gov> wrote:

> Here is the output:
>
> before scan bus of PCI: 00:18.0
> amdk8_scan_chains: PCI: 00:18.0, node 0
> amdk8_scan_chains: PCI: 00:18.0, node 0, link 0
> amdk8_scan_chain: PCI: 00:18.0, node 0, link 0
> connected
> Init Complete
> non coherent
> scan chain
> ht_collapse_early_enumeration: PCI: 00:18.0 children PCI: 00:18.0
> offset_unitid0
> ht_collapse_early_enumeration: ctrl = 20
> Check collapse state
> Check collapse state pci_read
> pci_remember_direct: pci_bus_fallback_ops=00000000
> pci_check_direct

It looks like it's dying in pci_check_direct.  Hopefully we're getting
close.  Here's another patch.

Thanks,
Myles
Hugh Greenberg - 2009-10-21 21:03:44
Alight!  It booted and loaded seabios.  Attached is the entire output.  
One thing though, it failed to load gpxe.  The only thing related to 
this that looks like an error is:

File pci14e4,16a6.rom is of type 63000000 instead oftype 30
and this
PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect Expansion ROM Header Signature 0000

I got this file from gpxe's rom O matic.  I tried getting a new one just 
in case and got the same error.
Peter Stuge - 2009-10-22 00:16:11
Hugh Greenberg wrote:
> File pci14e4,16a6.rom is of type 63000000 instead oftype 30
> and this
> PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
> Incorrect Expansion ROM Header Signature 0000
>
> I got this file from gpxe's rom O matic.  I tried getting a new one
> just in case and got the same error.

IIRC this is a known problem (by us) but there hasn't been much
effort in getting it fixed with GPXE. There is a script in the
SeaBIOS source tree which can fix up checksums, maybe you can try
using that - and if it works send a hint to GPXE?


//Peter
Kevin O'Connor - 2009-10-22 00:28:30
On Wed, Oct 21, 2009 at 03:03:44PM -0600, Hugh Greenberg wrote:
> Alight!  It booted and loaded seabios.  Attached is the entire output.   
> One thing though, it failed to load gpxe.  The only thing related to  
> this that looks like an error is:
>
> File pci14e4,16a6.rom is of type 63000000 instead oftype 30
> and this
> PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
> Incorrect Expansion ROM Header Signature 0000
>
> I got this file from gpxe's rom O matic.  I tried getting a new one just  
> in case and got the same error.

Please compile SeaBIOS with the debug level set to 8 (#define
CONFIG_DEBUG_LEVEL 8 in src/config.h) and then resend the full output.

-Kevin
Hugh Greenberg - 2009-10-29 18:21:53
The script didn't help.  Seabios just doesn't see the rom.  Is this a 
seabios problem?  I didn't have this problem for the tyan s2881.  Here 
is the output again:

PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect Expansion ROM Header Signature 0000
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 5 resources
PCI: 00:18.0: enabled 1, 4 resources
PCI: 01:01.0: enabled 1, 3 resources
PCI: 01:01.1: enabled 1, 1 resources
PCI: 01:02.0: enabled 0, 0 resources
PCI: 01:02.1: enabled 1, 1 resources
PCI: 01:03.0: enabled 1, 3 resources
PCI: 04:00.0: enabled 1, 1 resources
PCI: 04:00.1: enabled 1, 1 resources
PCI: 04:00.2: enabled 0, 0 resources
PCI: 04:01.0: enabled 0, 0 resources
PCI: 04:06.0: enabled 1, 4 resources
PCI: 01:04.0: enabled 1, 3 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 0, 3 resources
PNP: 002e.2: enabled 0, 4 resources
PNP: 002e.3: enabled 1, 2 resources
PNP: 002e.4: enabled 0, 2 resources
PNP: 002e.5: enabled 0, 1 resources
PNP: 002e.6: enabled 1, 3 resources
PNP: 002e.7: enabled 0, 2 resources
PNP: 002e.8: enabled 0, 2 resources
PNP: 002e.9: enabled 0, 2 resources
PNP: 002e.a: enabled 0, 2 resources
PCI: 01:04.1: enabled 1, 1 resources
PCI: 01:04.2: enabled 1, 1 resources
PCI: 01:04.3: enabled 1, 1 resources
I2C: 01:70: enabled 1, 0 resources
I2C: 00:2c: enabled 1, 0 resources
I2C: 01:50: enabled 1, 0 resources
I2C: 01:51: enabled 1, 0 resources
I2C: 01:52: enabled 1, 0 resources
I2C: 01:53: enabled 1, 0 resources
I2C: 01:54: enabled 1, 0 resources
I2C: 01:55: enabled 1, 0 resources
I2C: 01:56: enabled 1, 0 resources
I2C: 01:57: enabled 1, 0 resources
PCI: 01:04.5: enabled 0, 0 resources
PCI: 01:04.6: enabled 1, 2 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 1 resources
PCI: 00:19.0: enabled 1, 0 resources
PCI: 00:19.1: enabled 1, 0 resources
PCI: 00:19.2: enabled 1, 0 resources
PCI: 00:19.3: enabled 1, 0 resources
APIC: 01: enabled 1, 0 resources
PCI: 02:03.0: enabled 1, 2 resources
PCI: 02:04.0: enabled 1, 2 resources
Initializing CBMEM area to 0x3fff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 3fff0200...ok
High Tables Base is 3fff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x3fff0400... done.
PIRQ table: 176 bytes.
Looking for bad PCIX MHz input
Looking for bad Hot Swap Enable
OK 133MHz & Hot Swap is off
Wrote the mp table end at: 000f0410 - 000f0614
Adding CBMEM entry as no. 3
Looking for bad PCIX MHz input
Looking for bad Hot Swap Enable
OK 133MHz & Hot Swap is off
Wrote the mp table end at: 3fff1410 - 3fff1614
MP table: 532 bytes.
Adding CBMEM entry as no. 4
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum 9bdf
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x3fff2400
rom_table_end = 0x3fff2400
Adjust low_table_end from 0x00000518 to 0x00001000
Adjust rom_table_end from 0x3fff2400 to 0x40000000
Adding high table area
Wrote coreboot table at: 3fff2400 - 3fff2ca4  checksum b5b9
coreboot table: 2212 bytes.
 0. FREE SPACE 3fff4400 0000bc00
 1. GDT        3fff0200 00000200
 2. IRQ TABLE  3fff0400 00001000
 3. SMP TABLE  3fff1400 00001000
 4. COREBOOT   3fff2400 00002000
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + a590 + align -> fff8a600
Check fallback/payload
Got a payload
Loading segment from rom address 0xfff8a638
  data (compression=1)
malloc Enter, size 36, free_mem_ptr 00160ce4
malloc 00160ce4
  New segment dstaddr 0xf0000 memsize 0x10000 srcaddr 0xfff8a670 
filesize 0x7350
  (cleaned up) New segment addr 0xf0000 size 0x10000 offset 0xfff8a670 
filesize0
Loading segment from rom address 0xfff8a654
  Entry Point 0x000fc4f3
Loading Segment: addr: 0x00000000000f0000 memsz: 0x0000000000010000 
filesz: 0x00
lb: [0x0000000000100000, 0x0000000000164000)
Post relocation: addr: 0x00000000000f0000 memsz: 0x0000000000010000 
filesz: 0x00
using LZMA
[ 0x00000000000f0000, 0000000000100000, 0x0000000000100000) <- 
00000000fff8a670
dest f0000, end 100000, bouncebuffer 7ff38000
Loaded segments
Jumping to boot code at fc4f3
entry    = 0x000fc4f3
lb_start = 0x00100000
lb_size  = 0x00064000
adjust   = 0x7fe9c000
buffer   = 0x7ff38000
     elf_boot_notes = 0x00113a20
adjusted_boot_notes = 0x7ffafa20
Start bios (version 0.4.2-20090908_202836-morn.localdomain)
CPU Mhz=1804
Found mainboard Arima HDAMA
Found CBFS header at 0xfffeffe0
Ram Size=0x80000000
Found 2 cpu(s)
Scan for VGA option rom
Got ps2 nak (status=51); continuing
ps2_recvbyte timeout
Found 0 lpt ports
Found 1 serial ports
Copying PIR from 0x3fff0400 to 0x000fdc50
Copying MPTABLE from 0x3fff1400/3fff1410 to 0x000fda30
SMBIOS ptr=0x000fda10 table=0x7ffff800

Scan for option roms
Press F12 for boot menu.

Returned 61440 bytes of ZoneHigh
e820 map has 7 items:
  0: 0000000000000000 - 000000000009f400 = 1
  1: 000000000009f400 - 00000000000a0000 = 2
  2: 00000000000f0000 - 0000000000100000 = 2
  3: 0000000000100000 - 000000003fff0000 = 1
  4: 000000003fff0000 - 0000000040000000 = 2
  5: 0000000040000000 - 000000007ffff000 = 1
  6: 000000007ffff000 - 0000000080000000 = 2
enter handle_19:
  NULL
Booting from Floppy...
fail handle_legacy_disk:845(1):
   a=00000201  b=00000000  c=00000001  d=00000000 ds=0000 es=07c0 ss=0000
  si=00000000 di=00000000 bp=00000000 sp=00007b18 cs=f000 ip=e82d  f=0002
Boot failed: could not read the boot disk

enter handle_18:
  NULL
Booting from CD-Rom...
Boot failed: Could not read from CDROM (code 0001)
enter handle_18:
  NULL
Booting from Hard Disk...
fail handle_legacy_disk:845(1):
   a=00000201  b=00000000  c=00000001  d=00000080 ds=0000 es=07c0 ss=0000
  si=00000000 di=00000000 bp=00000000 sp=00007b18 cs=f000 ip=e82d  f=0002
Boot failed: could not read the boot disk

enter handle_18:
  NULL
Booting from CBFS...
enter handle_18:
  NULL
No bootable device.

 CTRL-A Z for help |115200 8N1 | NOR | Minicom 2.3    | VT102 |      
Offline
Myles Watson - 2009-10-29 19:01:49
On Thu, Oct 29, 2009 at 12:21 PM, Hugh Greenberg <hng@lanl.gov> wrote:

> The script didn't help.  Seabios just doesn't see the rom.  Is this a
> seabios problem?  I didn't have this problem for the tyan s2881.  Here is
> the output again:
>


> Found mainboard Arima HDAMA
> Found CBFS header at 0xfffeffe0
> Ram Size=0x80000000
> Found 2 cpu(s)
> Scan for VGA option rom
>
Here's a snippet from mine:

Scan for VGA option rom
Attempting to init PCI bdf 02:00.0 (dev/ven 014110de)
Searching CBFS for prefix pci10de,0141.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file
...
Much later
...
Scan for option roms
Attempting to init PCI bdf 00:00.0 (dev/ven 005e10de)
Searching CBFS for prefix pci10de,005e.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file
Attempting to map option rom on dev 00:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:01.0 (dev/ven 005110de)
Searching CBFS for prefix pci10de,0051.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file

Is your debug level >= 6 for SeaBIOS?  It looks like you do.

Do you have CONFIG_OPTION_ROMS_DEPLOYED set to 0?

Thanks,
Myles
Hugh Greenberg - 2009-10-29 20:01:59
I was using the pre-built one mentioned in the wiki: 
http://www.coreboot.org/SeaBIOS .  I don't know what the debug option is 
set to.  This worked for me for the tyan s2881, so I assume that the 
correct options are set.  I tried compiling my own and I had that option 
set along with the others mentioned in the wiki, but I also had the same 
problem.  I can try compiling my own again and making sure the debug 
option is set to 6.
Hugh Greenberg - 2009-10-29 20:31:53
Here is the relevant output with the debug option set to 6:

Searching CBFS for prefix floppyimg/
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
Scan for option roms
Attempting to init PCI bdf 00:18.0 (dev/ven 11001022)
Searching CBFS for prefix pci1022,1100.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
Attempting to map option rom on dev 00:18.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.1 (dev/ven 11011022)
Searching CBFS for prefix pci1022,1101.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
Attempting to map option rom on dev 00:18.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.2 (dev/ven 11021022)
Searching CBFS for prefix pci1022,1102.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
Attempting to map option rom on dev 00:18.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.3 (dev/ven 11031022)
Searching CBFS for prefix pci1022,1103.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
Attempting to map option rom on dev 00:18.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.0 (dev/ven 11001022)
Searching CBFS for prefix pci1022,1100.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
Attempting to map option rom on dev 00:19.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.1 (dev/ven 11011022)
Searching CBFS for prefix pci1022,1101.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom

Los Alamos National Laboratory, CCS-1
Email: hng@lanl.gov
Phone: (505) 665-6471

Found CBFS file
Attempting to map option rom on dev 00:19.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.2 (dev/ven 11021022)
Searching CBFS for prefix pci1022,1102.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
Attempting to map option rom on dev 00:19.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.3 (dev/ven 11031022)
Searching CBFS for prefix pci1022,1103.rom
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
Attempting to map option rom on dev 00:19.3
Option rom sizing returned 0 0
Searching CBFS for prefix genroms/
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
Press F12 for boot menu.

finalize PMM
malloc finalize
zone 0: 00007c00-00090000 used=0 (0%)
zone 1: 000a0000-000a0000 used=0 (0%)
zone 2: 000fd440-000fdc40 used=752 (36%)
zone 3: 40000000-7fff0000 used=128 (0%)
zone 4: 7fff0000-80000000 used=2048 (3%)
Returned 61440 bytes of ZoneHigh
e820 map has 7 items:
  0: 0000000000000000 - 000000000009f400 = 1
  1: 000000000009f400 - 00000000000a0000 = 2
  2: 00000000000f0000 - 0000000000100000 = 2
  3: 0000000000100000 - 000000003fff0000 = 1
  4: 000000003fff0000 - 0000000040000000 = 2
  5: 0000000040000000 - 000000007ffff000 = 1
  6: 000000007ffff000 - 0000000080000000 = 2
Jump to int19
enter handle_19:
  NULL
Booting from Floppy...
fail handle_legacy_disk:801(1):
   a=00000201  b=00000000  c=00000001  d=00000000 ds=0000 es=07c0 ss=0000
  si=00000000 di=00000000 bp=00000000 sp=00007b00 cs=f000 ip=efc4  f=0202
Boot failed: could not read the boot disk

enter handle_18:
  NULL
Booting from CD-Rom...
Boot failed: Could not read from CDROM (code 0001)
enter handle_18:
  NULL
Booting from Hard Disk...
fail handle_legacy_disk:801(1):
   a=00000201  b=00000000  c=00000001  d=00000080 ds=0000 es=07c0 ss=0000
  si=00000000 di=00000000 bp=00000000 sp=00007b00 cs=f000 ip=efc4  f=0202
Boot failed: could not read the boot disk

enter handle_18:
  NULL
Booting from CBFS...
Searching CBFS for prefix img/
Found CBFS file fallback/coreboot_ram
Found CBFS file fallback/payload
Found CBFS file pci14e4,16a6.rom
Found CBFS file
enter handle_18:
  NULL
No bootable device.


It seems though that seabios does not detect my network cards.  I tried 
then adding the rom as pci1022,1101.rom, and gpxe will load, but it 
won't detect my network devices.  Any suggestions?  Thanks.
Myles Watson - 2009-10-29 20:52:51
On Thu, Oct 29, 2009 at 2:31 PM, Hugh Greenberg <hng@lanl.gov> wrote:

> Here is the relevant output with the debug option set to 6:
>
> Searching CBFS for prefix floppyimg/
>
> Found CBFS file fallback/coreboot_ram
> Found CBFS file fallback/payload
> Found CBFS file pci14e4,16a6.rom
> Found CBFS file
> Scan for option roms
> Attempting to init PCI bdf 00:18.0 (dev/ven 11001022)
>
...

> Attempting to init PCI bdf 00:18.1 (dev/ven 11011022)
>
...

> Attempting to init PCI bdf 00:18.2 (dev/ven 11021022)
>
Attempting to init PCI bdf 00:18.3 (dev/ven 11031022)
> Attempting to init PCI bdf 00:19.0 (dev/ven 11001022)
> Attempting to init PCI bdf 00:19.1 (dev/ven 11011022)
> Attempting to init PCI bdf 00:19.2 (dev/ven 11021022)
> Attempting to init PCI bdf 00:19.3 (dev/ven 11031022)

It's only seeing your CPUs.  I was looking for Attempting to init... lines
with other devices.

02:03.0 (from your Coreboot log this looks like one of your NICs)

Maybe you can cheat and set CONFIG_PCI_ROOT1 to 2.  I don't know why it's
not finding your devices.

Thanks,
Myles

Patch

Index: svn/src/devices/pci_device.c
===================================================================
--- svn.orig/src/devices/pci_device.c
+++ svn/src/devices/pci_device.c
@@ -1081,7 +1081,9 @@  unsigned int pci_scan_bus(struct bus *bu
 	 * scan the bus behind that child.
 	 */
 	for (child = bus->children; child; child = child->sibling) {
+		printk_debug("before scan bus of %s\n", dev_path(child));
 		max = scan_bus(child, max);
+        printk_debug("after scan bus of %s\n", dev_path(child));
 	}
 
 	/* We've scanned the bus and so we know all about what's on the other
Index: svn/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- svn.orig/src/northbridge/amd/amdk8/northbridge.c
+++ svn/src/northbridge/amd/amdk8/northbridge.c
@@ -93,19 +93,29 @@  static unsigned int amdk8_scan_chain(dev
 		unsigned min_bus;
 		unsigned max_devfn;
 
+		printk_debug("%s: %s, node %d, link %d\n", __func__,
+			     dev_path(dev), nodeid, link);
+
 		dev->link[link].cap = 0x80 + (link *0x20);
+		if (pci_read_config32(dev, dev->link[link].cap + 0x18) &
+		    ConnectionPending)
+			printk_debug("%s: connection pending %s link %d\n",
+				      __func__, dev_path(dev), link);
 		do {
 			link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
 		} while(link_type & ConnectionPending);
 		if (!(link_type & LinkConnected)) {
 			return max;
 		}
+		printk_debug("connected\n");
 		do {
 			link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
 		} while(!(link_type & InitComplete));
+		printk_debug("Init Complete\n");
 		if (!(link_type & NonCoherent)) {
 			return max;
 		}
+		printk_debug("non coherent\n");
 		/* See if there is an available configuration space mapping
 		 * register in function 1.
 		 */
@@ -199,6 +209,7 @@  static unsigned int amdk8_scan_chain(dev
 		else
 			max_devfn = (0x1f<<3) | 7;
 
+		printk_debug("scan chain\n");
 		max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
 
 		/* We know the number of busses behind this bridge.  Set the
@@ -237,6 +248,8 @@  static unsigned int amdk8_scan_chains(de
 	unsigned offset_unitid = 0;
 	nodeid = amdk8_nodeid(dev);
 
+	printk_debug("%s: %s, node %d\n", __func__,
+		     dev_path(dev), nodeid);
 	if(nodeid==0) {
 		sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
@@ -248,6 +261,8 @@  static unsigned int amdk8_scan_chains(de
 	}
 
 	for(link = 0; link < dev->links; link++) {
+		printk_debug("%s: %s, node %d, link %d\n", __func__,
+			     dev_path(dev), nodeid, link);
 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 		if( (nodeid == 0) && (sblink == link) ) continue; //already done
 #endif
Index: svn/src/devices/hypertransport.c
===================================================================
--- svn.orig/src/devices/hypertransport.c
+++ svn/src/devices/hypertransport.c
@@ -299,6 +299,11 @@  static void ht_collapse_early_enumeratio
 	prev.freq_off     = PCI_HT_CAP_HOST_FREQ;
 	prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
 
+	printk_debug("%s: %s children %s offset_unitid %d\n", __func__,
+		     dev_path(bus->dev), dev_path(bus->children), offset_unitid);
+	printk_debug("%s: ctrl = %x\n", __func__,
+		     pci_read_config16(prev.dev, prev.pos + prev.ctrl_off));
+
 	/* Wait until the link initialization is complete */
 	do {
 		ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
@@ -332,6 +337,7 @@  static void ht_collapse_early_enumeratio
         }
 #endif
 
+	printk_debug("Check collapse state\n");
         /* Check if is already collapsed */
         if((!offset_unitid)|| (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) {
                 struct device dummy;
@@ -339,7 +345,9 @@  static void ht_collapse_early_enumeratio
                 dummy.bus              = bus;
                 dummy.path.type        = DEVICE_PATH_PCI;
                 dummy.path.pci.devfn = PCI_DEVFN(0, 0);
+		printk_debug("Check collapse state pci_read\n");
                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
+		printk_debug("Check collapse state after pci_read\n");
                 if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
                     (id == 0x0000ffff) || (id == 0xffff0000) ) ) {
                              return;
@@ -349,6 +357,7 @@  static void ht_collapse_early_enumeratio
 	/* Spin through the devices and collapse any early
 	 * hypertransport enumeration.
 	 */
+	printk_debug("Collapsing devs\n");
 	for(devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) {
 		struct device dummy;
 		uint32_t id;
@@ -356,7 +365,9 @@  static void ht_collapse_early_enumeratio
 		dummy.bus              = bus;
 		dummy.path.type        = DEVICE_PATH_PCI;
 		dummy.path.pci.devfn = devfn;
+		printk_debug("Collapse state pci_read\n");
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
+		printk_debug("After collapse state pci_read\n");
 		if (	(id == 0xffffffff) || (id == 0x00000000) || 
 			(id == 0x0000ffff) || (id == 0xffff0000)) {
 			continue;
@@ -376,6 +387,7 @@  static void ht_collapse_early_enumeratio
 		printk_spew("Collapsing %s [%04x/%04x]\n", 
 			dev_path(&dummy), dummy.vendor, dummy.device);
 	}
+	printk_debug("Done collapsing devs\n");
 }
 
 unsigned int hypertransport_scan_chain(struct bus *bus, 
@@ -401,6 +413,8 @@  unsigned int hypertransport_scan_chain(s
 	/* Restore the hypertransport chain to it's unitialized state */
 	ht_collapse_early_enumeration(bus, offset_unitid);
 
+	printk_debug("%s: %s children %s offset_unitid %d\n", __func__,
+		     dev_path(bus->dev), dev_path(bus->children), offset_unitid);
 	/* See which static device nodes I have */
 	old_devices = bus->children;
 	bus->children = 0;
@@ -449,10 +463,13 @@  unsigned int hypertransport_scan_chain(s
 			}
 		} while((ctrl & (1 << 5)) == 0);
 		
+		printk_debug("%s: link OK\n", __func__);
 
 		/* Get and setup the device_structure */
 		dev = ht_scan_get_devs(&old_devices);
 
+		printk_debug("%s: dev = %s\n", dev_path(dev));
+		printk_debug("%s: old_devs = %s\n", dev_path(old_devices));
 		/* See if a device is present and setup the
 		 * device structure.
 		 */
Index: svn/src/arch/i386/lib/pci_ops_auto.c
===================================================================
--- svn.orig/src/arch/i386/lib/pci_ops_auto.c
+++ svn/src/arch/i386/lib/pci_ops_auto.c
@@ -47,6 +47,9 @@  const struct pci_bus_operations *pci_che
 {
 	unsigned int tmp;
 
+	printk_debug("%s\n", __func__);
+	printk_debug("PCI: Forcing configuration type 1\n");
+	return &pci_cf8_conf1;
 	/*
 	 * Check if configuration type 1 works.
 	 */
@@ -85,6 +88,8 @@  const struct pci_bus_operations *pci_che
 
 const struct pci_bus_operations *pci_remember_direct(void)
 {
+	printk_debug("%s: pci_bus_fallback_ops=%p\n", __func__,
+		     pci_bus_fallback_ops);
 	if (!pci_bus_fallback_ops)
 		pci_bus_fallback_ops = pci_check_direct();
 	return pci_bus_fallback_ops;