Patchwork [Fwd:,Re:,[Fwd:,Re:,[Fwd:,Re:,arima,hdama,problem] ]]

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Submitter Myles Watson
Date 2009-10-21 21:35:56
Message ID <2831fecf0910211435i774fb8a0jadb5a28f407d6912@mail.gmail.com>
Download mbox | patch
Permalink /patch/458/
State Superseded
Headers show

Comments

Myles Watson - 2009-10-21 21:35:56
On Wed, Oct 21, 2009 at 3:03 PM, Hugh Greenberg <hng@lanl.gov> wrote:

> Alight!  It booted and loaded seabios.  Attached is the entire output.

Great.  So the two problems were init_timer and pci_check_direct, right?

I've attached the two patches.

Signed-off-by: Myles Watson <mylesgw@gmail.com>


>  One thing though, it failed to load gpxe.  The only thing related to this
> that looks like an error is:
>
> File pci14e4,16a6.rom is of type 63000000 instead oftype 30
> and this
> PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
> Incorrect Expansion ROM Header Signature 0000
>
This should be OK because you don't want it to run before Coreboot is
through.  I think SeaBIOS should run it, right?

I don't know anything about gpxe.  I'm assuming you followed the
instructions here:
http://www.coreboot.org/SeaBIOS#Adding_gpxe_support

Did you try pushing f12 to see the boot menu?

Thanks,
Myles
Hugh Greenberg - 2009-10-21 21:54:46
Yeah, those two patches solved the problem.  Thank you very much for 
your help with this.  I followed those directions, but still no luck. 
I'll keep working at it.
Hugh Greenberg - 2009-10-21 22:18:34
While I was just trying to get seabios to boot gpxe, coreboot hung at 
the same spot.  It seems to happen randomly now, not every time it boots 
like before.
Myles Watson - 2009-10-21 22:20:46
> While I was just trying to get seabios to boot gpxe, coreboot hung at
> the same spot.  It seems to happen randomly now, not every time it boots
> like before.
Too bad.

I guess put all the debugging back in and see if it still hangs randomly,
and if it is exactly the same spot.

Thanks,
Myles
Hugh Greenberg - 2009-10-21 23:37:41
I'm having a hard time reproducing it now. I'll post something when/if I 
have the output with the debug info.
Hugh Greenberg - 2009-10-22 15:09:25
It froze again.  Here is some of the output:

SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
setting up CPU01 northbridge registers
done.
Ram2.00
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00100000 kB
Lower RAM end at 0x00100000 kB
Ram2.01
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00200000 kB
Lower RAM end at 0x00200000 kB
Ram3
Before starting clocks: Before memreset: cpu is pre_c0
after first udelay
Myles Watson - 2009-10-22 15:16:14
> RAM end at 0x00200000 kB
> Lower RAM end at 0x00200000 kB
> Ram3
> Before starting clocks: Before memreset: cpu is pre_c0
> after first udelay

OK.  So the timer worked for the first udelay...

Does it only freeze when you have both CPUs enabled?  Have you tried it with
the no_smp patch again?  I'm grasping at straws.

Thanks,
Myles
Ward Vandewege - 2009-10-22 15:35:37
On Thu, Oct 22, 2009 at 09:16:14AM -0600, Myles Watson wrote:
> > RAM end at 0x00200000 kB
> > Lower RAM end at 0x00200000 kB
> > Ram3
> > Before starting clocks: Before memreset: cpu is pre_c0
> > after first udelay
> 
> OK.  So the timer worked for the first udelay...
> 
> Does it only freeze when you have both CPUs enabled?  Have you tried it with
> the no_smp patch again?  I'm grasping at straws.

This is starting to sound like all the weirdness I was seeing when working on
the h8dmr fam10 port a few months ago.

Are you sure it hangs? I thought so at first as well, but it turned out that
things were running extremely slowly when compiling with gcc 4.3 (32 bit). If
I waited 5 minutes or so eventually the board would boot.

Can you reproduce a hang when changing CONSOLE_LOGLEVEL ? In my case the
board would just hang if I lowered the default loglevel to something less
than 8.

I never did figure out what was going on there. Ron thought perhaps there was
a cache issue. I put a file in the tree with the issues I ran into

  src/mainboard/supermicro/h8dmr_fam10/README

I haven't been able to revisit yet as that particular box is in production.

What toolchain are you using? 

Thanks,
Ward.
Hugh Greenberg - 2009-10-29 18:19:52
I was using gcc 4.3.  Without the patches, I still see a problem even 
with gcc 3.4.  With the patches and gcc 3.4, things seem to be better so 
far.  Thanks.

Patch

Index: svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/arima/hdama/cache_as_ram_auto.c
+++ svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
@@ -157,33 +157,22 @@  void cache_as_ram_main(unsigned long bis
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const struct mem_controller cpu[] = {
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
+	static const uint16_t spd_addr [] = {
+		(0xa<<3)|0, (0xa<<3)|2, 0, 0,
+		(0xa<<3)|1, (0xa<<3)|3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
+		(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+		(0xa<<3)|5, (0xa<<3)|7, 0, 0,
 #endif
 	};
 
         int needs_reset;
+	unsigned bsp_apicid = 0;
+	struct mem_controller ctrl[8];
+	unsigned nodes;
 
         if (bist == 0) {
-		init_cpus(cpu_init_detectedx);
+		bsp_apicid = init_cpus(cpu_init_detectedx);
         }
 
 	pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -200,7 +189,10 @@  void real_main(unsigned long bist, unsig
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
         start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
 #endif
+	init_timer();  /* This is needed to be able to call udelay() */
+
         // automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
 
@@ -209,11 +201,17 @@  void real_main(unsigned long bist, unsig
                	soft_reset();
        	}
 
+	allow_all_aps_stop(bsp_apicid);
+
+	nodes = get_nodes();
+
+	fill_mem_ctrl(nodes, ctrl, spd_addr);
+
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
-	post_cache_as_ram();
+	sdram_initialize(nodes, ctrl);
 
+	post_cache_as_ram();
 }