Patchwork PCI config

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Submitter Myles Watson
Date 2009-10-22 16:13:15
Message ID <2831fecf0910220913jb7467ealc65b677b744bd5e2@mail.gmail.com>
Download mbox | patch
Permalink /patch/462/
State New
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Comments

Myles Watson - 2009-10-22 16:13:15
On Thu, Oct 22, 2009 at 9:45 AM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006@gmx.net> wrote:

> On 22.10.2009 09:57, Stefan Reinauer wrote:
> > Myles Watson wrote:
> >
> >> The attached patch fixes booting for arima/hdama.
> >>
> >> How should we really fix it?  In v3 didn't we just scrap type 2
> >> accesses all together?
> >>
> > We can keep the type 2 support code, but the auto detection at run time
> > makes absolutely no sense.
> >
> > I sent a patch for this some days ago, but I think Carl-Daniel didn't
> > have too much success with it on his board.
> >
>
> Yes, if I applied the complete patch, the board was hanging. If I
> applied parts of the patch (the rs690 part), the board still was
> hanging, but I think that was due to a device tree code bug/limitation.
> I can dig up the details if you want, becase the patch itself looked
> desirable.
>
What if you just take out the init call in the enable function?

Modified patch attached.

Thanks,
Myles

Patch

Simplify coreboot PCI handling

This patch drops the conf1/conf2 autodetection and replaces it by 
(usually northbridge specific) hardcodes. 

This patch also adds pci_domain_init() which needs to be called by
mainboard enable_dev() functions in order to be able to use the pci
config space functions. This allows to drop i386 specific code from
generic files again...

There is an even better approach to the PCI config space access in mainboard
specific init files problem, but that should go into another patch:

static void init(struct device *dev)
{
	// Do the stuff here!
}

static void enable_dev(struct device *dev)
{
   // Install an init function for this mainboard device
   dev->ops->init = init;
}

struct chip_operations mainboard_ops = {
  .enable_dev = enable_dev,
};

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>



Index: svn/src/southbridge/amd/rs690/rs690.c
===================================================================
--- svn.orig/src/southbridge/amd/rs690/rs690.c
+++ svn/src/southbridge/amd/rs690/rs690.c
@@ -37,34 +37,33 @@  void static rs690_config_misc_clk(device
 {
 	u32 reg;
 	u16 word;
-	/* u8 byte; */
-	struct bus pbus; /* fake bus for dev0 fun1 */
+	device_t nb2_dev = dev_find_slot(0, PCI_DEVFN(0, 1));
 
 	reg = pci_read_config32(nb_dev, 0x4c);
 	reg |= 1 << 0;
 	pci_write_config32(nb_dev, 0x4c, reg);
 
-	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
+	word = pci_read_config16(nb2_dev, 0xf8);
 	word &= 0xf00;
-	pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
+	pci_write_config16(nb2_dev, 0xf8, word);
 
-	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
+	word = pci_read_config16(nb2_dev, 0xe8);
 	word &= ~((1 << 12) | (1 << 13) | (1 << 14));
 	word |= 1 << 13;
-	pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
+	pci_write_config16(nb2_dev, 0xe8, word);
 
-	reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+	reg = pci_read_config32(nb2_dev, 0x94);
 	reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+	pci_write_config32(nb2_dev, 0x94, reg);
 
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+	reg = pci_read_config32(nb2_dev, 0x8c);
 	reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
 	reg |= 1 << 13;
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+	pci_write_config32(nb2_dev, 0x8c, reg);
 
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+	reg = pci_read_config32(nb2_dev, 0xcc);
 	reg |= 1 << 24;
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+	pci_write_config32(nb2_dev, 0xcc, reg);
 
 	reg = nbmc_read_index(nb_dev, 0x7a);
 	reg &= ~0x3f;
@@ -72,26 +71,28 @@  void static rs690_config_misc_clk(device
 	reg &= ~(1 << 6);
 	set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
 	nbmc_write_index(nb_dev, 0x7a, reg);
+
 	/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+	reg = pci_read_config32(nb2_dev, 0xcc);
 	reg &= ~(1 << 23);
-	reg |= 1 << 24;
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+	reg |= 1 << 24; // already set?
+	pci_write_config32(nb2_dev, 0xcc, reg);
+
 #if 0
 	/* Powerdown reference clock to graphics core PLL in northbridge only mode */
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+	reg = pci_read_config32(nb2_dev, 0x8c);
 	reg |= 1 << 21;
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+	pci_write_config32(nb2_dev, 0x8c, reg);
 
 	/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
-	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+	reg = pci_read_config32(nb2_dev, 0xcc);
 	reg |= (1 << 23) | (1 << 24);
-	pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+	pci_write_config32(nb2_dev, 0xcc, reg);
 
 	/* Powerdown clock to memory controller in northbridge only mode */
-	byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
+	byte = pci_read_config8(nb2_dev, 0xe4);
 	byte |= 1 << 0;
-	pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
+	pci_write_config8(nb2_dev, 0xe4, reg);
 
 	/* CLKCFG:0xE8 Bit[17] = 0x1 	 Powerdown clock to IOC GFX block in no external graphics mode */
 	/* TODO: */
Index: svn/src/southbridge/amd/rs690/rs690_pcie.c
===================================================================
--- svn.orig/src/southbridge/amd/rs690/rs690_pcie.c
+++ svn/src/southbridge/amd/rs690/rs690_pcie.c
@@ -361,7 +361,7 @@  void config_gpp_core(device_t nb_dev, de
 void pcie_config_misc_clk(device_t nb_dev)
 {
 	u32 reg;
-	struct bus pbus; /* fake bus for dev0 fun1 */
+	device_t nb2_dev = dev_find_slot(0, PCI_DEVFN(0, 1));
 
 	reg = pci_read_config32(nb_dev, 0x4c);
 	reg |= 1 << 0;
@@ -374,9 +374,9 @@  void pcie_config_misc_clk(device_t nb_de
 		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
 
 		/* LCLK Clock Gating */
-		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+		reg =  pci_read_config32(nb2_dev, 0x94);
 		reg &= ~(1 << 16);
-		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+		pci_write_config32(nb2_dev, 0x94, reg);
 	}
 
 	if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
@@ -386,9 +386,9 @@  void pcie_config_misc_clk(device_t nb_de
 		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6);
 
 		/* LCLK Clock Gating */
-		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+		reg =  pci_read_config32(nb2_dev, 0x94);
 		reg &= ~(1 << 24);
-		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+		pci_write_config32(nb2_dev, 0x94, reg);
 	}
 
 	reg = pci_read_config32(nb_dev, 0x4c);
Index: svn/src/southbridge/intel/i82801gx/i82801gx_pci.c
===================================================================
--- svn.orig/src/southbridge/intel/i82801gx/i82801gx_pci.c
+++ svn/src/southbridge/intel/i82801gx/i82801gx_pci.c
@@ -68,13 +68,13 @@  static void ich_pci_dev_enable_resources
 	uint16_t command;
 
 	/* Set the subsystem vendor and device id for mainboard devices */
-	ops = ops_pci(dev);
-	if (dev->on_mainboard && ops && ops->set_subsystem) {
+	if (dev->on_mainboard && dev->ops  && dev->ops->ops_pci
+	    && dev->ops->ops_pci->set_subsystem) {
 		printk_debug("%s subsystem <- %02x/%02x\n",
 			dev_path(dev),
 			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
 			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
-		ops->set_subsystem(dev,
+		dev->ops->ops_pci->set_subsystem(dev,
 			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
 			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 	}
Index: svn/src/devices/root_device.c
===================================================================
--- svn.orig/src/devices/root_device.c
+++ svn/src/devices/root_device.c
@@ -174,7 +174,7 @@  void root_dev_reset(struct bus *bus)
  * should be fully usable as is.  However the chip_operations::enable_dev()
  * of a motherboard can override this if you want non-default behavior.
  */
-struct device_operations default_dev_ops_root = {
+const struct device_operations default_dev_ops_root = {
 	.read_resources   = root_dev_read_resources,
 	.set_resources    = root_dev_set_resources,
 	.enable_resources = root_dev_enable_resources,
Index: svn/src/devices/pci_device.c
===================================================================
--- svn.orig/src/devices/pci_device.c
+++ svn/src/devices/pci_device.c
@@ -602,11 +602,14 @@  void pci_dev_set_resources(struct device
 
 void pci_dev_enable_resources(struct device *dev)
 {
-	const struct pci_operations *ops;
+	const struct pci_operations *ops = NULL;
 	u16 command;
 
 	/* Set the subsystem vendor and device id for mainboard devices. */
-	ops = ops_pci(dev);
+	if (dev && dev->ops) {
+		ops = dev->ops->ops_pci;
+	}
+
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
 		printk_debug("%s subsystem <- %02x/%02x\n",
 			     dev_path(dev),
@@ -1198,6 +1201,31 @@  unsigned int pci_domain_scan_bus(device_
 	return max;
 }
 
+/**
+ * @brief Initialize PCI domain for early PCI accesses.
+ *
+ * The PCI domain is a sub device of the mainboard device. Some mainboards use
+ * PCI accesses in their enable_dev instead of their .ops->init, and thus the PCI
+ * domain is not yet initialized. Such behavior is strictly speaking wrong,
+ * but also convenient. The behavior can be fixed by running pci_domain_init()
+ * before doing the actual PCI accesses.
+ *
+ * @param mainboard_dev mainboard device
+ */
+
+void pci_domain_init(device_t mainboard_dev)
+{
+	device_t dev = mainboard_dev->link[0].children;
+
+	while (dev && (dev->path.type != DEVICE_PATH_PCI_DOMAIN))
+		dev=dev->sibling;
+
+	if (dev)
+		dev->chip_ops->enable_dev(dev);
+}
+
+
+
 #if CONFIG_PC80_SYSTEM == 1
 /**
  * 
Index: svn/src/devices/pci_ops.c
===================================================================
--- svn.orig/src/devices/pci_ops.c
+++ svn/src/devices/pci_ops.c
@@ -25,19 +25,27 @@ 
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 
-/* The only consumer of the return value of get_pbus() is ops_pci_bus().
- * ops_pci_bus() can handle being passed NULL and auto-picks working ops.
- */
+static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus)
+{
+	const struct pci_bus_operations *bops;
+	bops = NULL;
+	if (bus && bus->dev && bus->dev->ops) {
+		bops = bus->dev->ops->ops_pci_bus;
+	}
+	return bops;
+}
+
 static struct bus *get_pbus(device_t dev)
 {
 	struct bus *pbus = NULL;
 
 	if (!dev)
 		die("get_pbus: dev is NULL!\n");
-	else
-		pbus = dev->bus;
 
-	while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
+	pbus = dev->bus;
+
+	while(pbus && pbus->dev && pbus->dev->ops && ! pbus->dev->ops->ops_pci_bus) {
+		/* TODO explain how such a loop can happen */
 		if (pbus == pbus->dev->bus) {
 			printk_alert("%s in endless loop looking for a parent "
 				"bus with ops_pci_bus for %s, breaking out.\n",
@@ -46,6 +54,7 @@  static struct bus *get_pbus(device_t dev
 		}
 		pbus = pbus->dev->bus;
 	}
+
 	if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) {
 		/* This can happen before the device tree is set up completely. */
 		//printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev));
Index: svn/src/include/device/pci_ops.h
===================================================================
--- svn.orig/src/include/device/pci_ops.h
+++ svn/src/include/device/pci_ops.h
@@ -21,7 +21,4 @@  void pci_mmio_write_config16(device_t de
 void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val);
 #endif
 
-/* This function lives in pci_ops_auto.c */
-const struct pci_bus_operations *pci_remember_direct(void);
-
 #endif /* PCI_OPS_H */
Index: svn/src/include/device/device.h
===================================================================
--- svn.orig/src/include/device/device.h
+++ svn/src/include/device/device.h
@@ -142,9 +142,10 @@  void show_all_devs_resources(int debug_l
 #define DEVICE_IO_ALIGN 16 
 #define DEVICE_MEM_ALIGN 4096
 
-extern struct device_operations default_dev_ops_root;
+extern const struct device_operations default_dev_ops_root;
 void pci_domain_read_resources(struct device *dev);
 unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
+void pci_domain_init(device_t mainboard_dev);
 void root_dev_read_resources(device_t dev);
 void root_dev_set_resources(device_t dev);
 unsigned int scan_static_bus(device_t bus, unsigned int max);
Index: svn/src/include/device/pci.h
===================================================================
--- svn.orig/src/include/device/pci.h
+++ svn/src/include/device/pci.h
@@ -80,26 +80,4 @@  void pci_assign_irqs(unsigned bus, unsig
 #define PCI_IO_BRIDGE_ALIGN 4096
 #define PCI_MEM_BRIDGE_ALIGN (1024*1024)
 
-static inline const struct pci_operations *ops_pci(device_t dev)
-{
-	const struct pci_operations *pops;
-	pops = 0;
-	if (dev && dev->ops) {
-		pops = dev->ops->ops_pci;
-	}
-	return pops;
-}
-
-static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus)
-{
-	const struct pci_bus_operations *bops;
-	bops = 0;
-	if (bus && bus->dev && bus->dev->ops) {
-		bops = bus->dev->ops->ops_pci_bus;
-	}
-	if (!bops)
-		bops = pci_remember_direct();
-	return bops;
-}
-
 #endif /* PCI_H */
Index: svn/src/cpu/amd/sc520/sc520.c
===================================================================
--- svn.orig/src/cpu/amd/sc520/sc520.c
+++ svn/src/cpu/amd/sc520/sc520.c
@@ -215,6 +215,7 @@  static struct device_operations pci_doma
         .enable_resources = 0, //enable_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };
 
 #if 0
@@ -242,7 +243,6 @@  static void enable_dev(struct device *de
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
         }
 #if 0
 	/* This is never hit as none of the sc520 boards have
Index: svn/src/cpu/emulation/qemu-x86/northbridge.c
===================================================================
--- svn.orig/src/cpu/emulation/qemu-x86/northbridge.c
+++ svn/src/cpu/emulation/qemu-x86/northbridge.c
@@ -141,6 +141,7 @@  static struct device_operations pci_doma
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,
+	.ops_pci_bus		= &pci_cf8_conf1,
 };
 
 static void enable_dev(struct device *dev)
@@ -148,7 +149,6 @@  static void enable_dev(struct device *de
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
 	}
 }
 
Index: svn/src/northbridge/via/cx700/northbridge.c
===================================================================
--- svn.orig/src/northbridge/via/cx700/northbridge.c
+++ svn/src/northbridge/via/cx700/northbridge.c
@@ -137,6 +137,7 @@  static struct device_operations pci_doma
 	.enable_resources = enable_childrens_resources,
 	.init		  = 0,
 	.scan_bus	  = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };
 
 static void cpu_bus_init(device_t dev)
@@ -161,7 +162,6 @@  static void enable_dev(struct device *de
 	/* Our wonderful device model */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
 	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
 	}
Index: svn/src/northbridge/via/cn400/northbridge.c
===================================================================
--- svn.orig/src/northbridge/via/cn400/northbridge.c
+++ svn/src/northbridge/via/cn400/northbridge.c
@@ -284,6 +284,7 @@  static const struct device_operations pc
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
 	.scan_bus         = cn400_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };
 
 static void cpu_bus_init(device_t dev)
@@ -310,7 +311,6 @@  static void enable_dev(struct device *de
 	/* Set the operations if it is a special bus type. */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
 	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
 	}
Index: svn/src/northbridge/via/vx800/northbridge.c
===================================================================
--- svn.orig/src/northbridge/via/vx800/northbridge.c
+++ svn/src/northbridge/via/vx800/northbridge.c
@@ -185,6 +185,7 @@  static const struct device_operations pc
 	.enable_resources = enable_childrens_resources,
 	.init = 0,
 	.scan_bus = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };
 
 static void cpu_bus_init(device_t dev)
@@ -211,7 +212,6 @@  static void enable_dev(struct device *de
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
 	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
 	}
Index: svn/src/northbridge/via/cn700/northbridge.c
===================================================================
--- svn.orig/src/northbridge/via/cn700/northbridge.c
+++ svn/src/northbridge/via/cn700/northbridge.c
@@ -208,6 +208,7 @@  static const struct device_operations pc
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
 	.scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };
 
 static void cpu_bus_init(device_t dev)
@@ -234,7 +235,6 @@  static void enable_dev(struct device *de
 	/* Set the operations if it is a special bus type. */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
 	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
 	}
Index: svn/src/northbridge/via/vt8601/northbridge.c
===================================================================
--- svn.orig/src/northbridge/via/vt8601/northbridge.c
+++ svn/src/northbridge/via/vt8601/northbridge.c
@@ -149,6 +149,7 @@  static struct device_operations pci_doma
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };  
 
 static void cpu_bus_init(device_t dev)
@@ -173,7 +174,6 @@  static void enable_dev(struct device *de
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;
Index: svn/src/northbridge/via/vt8623/northbridge.c
===================================================================
--- svn.orig/src/northbridge/via/vt8623/northbridge.c
+++ svn/src/northbridge/via/vt8623/northbridge.c
@@ -295,6 +295,7 @@  static struct device_operations pci_doma
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };  
 
 static void cpu_bus_init(device_t dev)
@@ -321,7 +322,6 @@  static void enable_dev(struct device *de
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;
Index: svn/src/northbridge/amd/gx1/northbridge.c
===================================================================
--- svn.orig/src/northbridge/amd/gx1/northbridge.c
+++ svn/src/northbridge/amd/gx1/northbridge.c
@@ -172,6 +172,7 @@  static struct device_operations pci_doma
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };  
 
 static void cpu_bus_init(device_t dev)
@@ -199,7 +200,6 @@  static void enable_dev(struct device *de
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
         	printk_spew("DEVICE_PATH_PCI_DOMAIN\n");
                 dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
         	printk_spew("DEVICE_PATH_APIC_CLUSTER\n");
Index: svn/src/northbridge/amd/gx2/northbridge.c
===================================================================
--- svn.orig/src/northbridge/amd/gx2/northbridge.c
+++ svn/src/northbridge/amd/gx2/northbridge.c
@@ -455,6 +455,7 @@  static struct device_operations pci_doma
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };  
 
 static void cpu_bus_init(device_t dev)
@@ -501,7 +502,6 @@  static void enable_dev(struct device *de
 		do_vsmbios();
 		graphics_init();
 		dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
 		tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE;
 #if CONFIG_WRITE_HIGH_TABLES==1
 		/* Leave some space for ACPI, PIRQ and MP tables */
Index: svn/src/northbridge/amd/lx/northbridge.c
===================================================================
--- svn.orig/src/northbridge/amd/lx/northbridge.c
+++ svn/src/northbridge/amd/lx/northbridge.c
@@ -447,7 +447,6 @@  static void pci_domain_enable(device_t d
 	// print_conf();
 
 	graphics_init();
-	pci_set_method(dev);
 }
 
 static struct device_operations pci_domain_ops = {
@@ -456,6 +455,7 @@  static struct device_operations pci_doma
 	.enable_resources = enable_childrens_resources,
 	.scan_bus = pci_domain_scan_bus,
 	.enable = pci_domain_enable,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };
 
 static void cpu_bus_init(device_t dev)
Index: svn/src/northbridge/intel/i855gme/northbridge.c
===================================================================
--- svn.orig/src/northbridge/intel/i855gme/northbridge.c
+++ svn/src/northbridge/intel/i855gme/northbridge.c
@@ -144,6 +144,7 @@  static struct device_operations pci_doma
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };  
 
 static void cpu_bus_init(device_t dev)
@@ -170,7 +171,6 @@  static void enable_dev(struct device *de
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;
Index: svn/src/northbridge/intel/i855pm/northbridge.c
===================================================================
--- svn.orig/src/northbridge/intel/i855pm/northbridge.c
+++ svn/src/northbridge/intel/i855pm/northbridge.c
@@ -112,6 +112,7 @@  static struct device_operations pci_doma
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };  
 
 static void cpu_bus_init(device_t dev)
@@ -138,7 +139,6 @@  static void enable_dev(struct device *de
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;
Index: svn/src/northbridge/intel/i440bx/northbridge.c
===================================================================
--- svn.orig/src/northbridge/intel/i440bx/northbridge.c
+++ svn/src/northbridge/intel/i440bx/northbridge.c
@@ -128,6 +128,7 @@  static struct device_operations pci_doma
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };
 
 static void cpu_bus_init(device_t dev)
@@ -152,9 +153,7 @@  static void enable_dev(struct device *de
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
-	}
-	else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
 	}
 }
Index: svn/src/northbridge/intel/i82810/northbridge.c
===================================================================
--- svn.orig/src/northbridge/intel/i82810/northbridge.c
+++ svn/src/northbridge/intel/i82810/northbridge.c
@@ -187,6 +187,7 @@  static struct device_operations pci_doma
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_cf8_conf1,
 };
 
 static void cpu_bus_init(device_t dev)
@@ -213,7 +214,6 @@  static void enable_dev(struct device *de
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
 	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
 	}
Index: svn/src/northbridge/intel/i82830/northbridge.c
===================================================================
--- svn.orig/src/northbridge/intel/i82830/northbridge.c
+++ svn/src/northbridge/intel/i82830/northbridge.c
@@ -145,6 +145,7 @@  static struct device_operations pci_doma
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,
+	.ops_pci_bus		= &pci_cf8_conf1,
 };
 
 static void cpu_bus_init(device_t dev)
@@ -171,7 +172,6 @@  static void enable_dev(struct device *de
 	/* Set the operations if it is a special bus type. */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
 	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
 	}
Index: svn/src/arch/i386/include/arch/pci_ops.h
===================================================================
--- svn.orig/src/arch/i386/include/arch/pci_ops.h
+++ svn/src/arch/i386/include/arch/pci_ops.h
@@ -8,6 +8,4 @@  extern const struct pci_bus_operations p
 extern const struct pci_bus_operations pci_ops_mmconf;
 #endif
 
-void pci_set_method(device_t dev);
-
 #endif /* ARCH_I386_PCI_OPS_H */
Index: svn/src/arch/i386/lib/Makefile.inc
===================================================================
--- svn.orig/src/arch/i386/lib/Makefile.inc
+++ svn/src/arch/i386/lib/Makefile.inc
@@ -3,7 +3,6 @@  obj-y += cpu.o
 obj-y += pci_ops_conf1.o
 obj-y += pci_ops_conf2.o
 obj-y += pci_ops_mmconf.o
-obj-y += pci_ops_auto.o
 obj-y += exception.o
 
 initobj-y += printk_init.o
Index: svn/src/arch/i386/lib/Config.lb
===================================================================
--- svn.orig/src/arch/i386/lib/Config.lb
+++ svn/src/arch/i386/lib/Config.lb
@@ -7,7 +7,6 @@  object cpu.c
 object pci_ops_conf1.c
 object pci_ops_conf2.c
 object pci_ops_mmconf.c
-object pci_ops_auto.c
 object exception.c
 
 initobject printk_init.o
Index: svn/src/arch/i386/lib/pci_ops_auto.c
===================================================================
--- svn.orig/src/arch/i386/lib/pci_ops_auto.c
+++ /dev/null
@@ -1,100 +0,0 @@ 
-#include <stddef.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pciconf.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-/*
- * Before we decide to use direct hardware access mechanisms, we try to do some
- * trivial checks to ensure it at least _seems_ to be working -- we just test
- * whether bus 00 contains a host bridge (this is similar to checking
- * techniques used in XFree86, but ours should be more reliable since we
- * attempt to make use of direct access hints provided by the PCI BIOS).
- *
- * This should be close to trivial, but it isn't, because there are buggy
- * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
- */
-static int pci_sanity_check(const struct pci_bus_operations *o)
-{
-	uint16_t class, vendor;
-	unsigned bus;
-	int devfn;
-	struct bus pbus; /* Dummy device */
-#define PCI_CLASS_BRIDGE_HOST		0x0600
-#define PCI_CLASS_DISPLAY_VGA		0x0300
-#define PCI_VENDOR_ID_COMPAQ		0x0e11
-#define PCI_VENDOR_ID_INTEL		0x8086
-#define PCI_VENDOR_ID_MOTOROLA		0x1057
-
-	for (bus = 0, devfn = 0; devfn < 0x100; devfn++) {
-		class = o->read16(&pbus, bus, devfn, PCI_CLASS_DEVICE);
-		vendor = o->read16(&pbus, bus, devfn, PCI_VENDOR_ID);
-		if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
-			((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
-				(vendor == PCI_VENDOR_ID_MOTOROLA))) { 
-			return 1;
-		}
-	}
-	printk_err("PCI: Sanity check failed\n");
-	return 0;
-}
-
-struct pci_bus_operations *pci_bus_fallback_ops = NULL;
-
-const struct pci_bus_operations *pci_check_direct(void)
-{
-	unsigned int tmp;
-
-	/*
-	 * Check if configuration type 1 works.
-	 */
-	{
-		outb(0x01, 0xCFB);
-		tmp = inl(0xCF8);
-		outl(0x80000000, 0xCF8);
-		if ((inl(0xCF8) == 0x80000000) && 
-			pci_sanity_check(&pci_cf8_conf1)) 
-		{
-			outl(tmp, 0xCF8);
-			printk_debug("PCI: Using configuration type 1\n");
-			return &pci_cf8_conf1;
-		}
-		outl(tmp, 0xCF8);
-	}
-
-	/*
-	 * Check if configuration type 2 works.
-	 */
-	{
-		outb(0x00, 0xCFB);
-		outb(0x00, 0xCF8);
-		outb(0x00, 0xCFA);
-		if ((inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) &&
-			pci_sanity_check(&pci_cf8_conf2))
-		{
-			printk_debug("PCI: Using configuration type 2\n");
-			return &pci_cf8_conf2;
-		}
-	}
-
-	die("pci_check_direct failed\n");
-	return NULL;
-}
-
-const struct pci_bus_operations *pci_remember_direct(void)
-{
-	if (!pci_bus_fallback_ops)
-		pci_bus_fallback_ops = pci_check_direct();
-	return pci_bus_fallback_ops;
-}
-
-/** Set the method to be used for PCI, type I or type II
- */
-void pci_set_method(device_t dev)
-{
-	printk_info("Finding PCI configuration type.\n");
-	dev->ops->ops_pci_bus = pci_remember_direct();
-	post_code(0x5f);
-}