From patchwork Sat Oct 24 22:48:42 2009
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: usbdebug fixes for core / core 2
Date: Sat, 24 Oct 2009 22:48:42 -0000
From: Stefan Reinauer <stepan@coresystems.de>
X-Patchwork-Id: 479
Message-Id: <4AE3844A.3080709@coresystems.de>
To: coreboot <coreboot@coreboot.org>

See patch
Acked-by: Peter Stuge <peter@stuge.se>


Index: src/cpu/intel/model_6ex/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram.inc	(revision 4842)
+++ src/cpu/intel/model_6ex/cache_as_ram.inc	(working copy)
@@ -94,7 +94,6 @@
 	//movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl
-#endif
 
 	/* Enable Cache As RAM mode by disabling cache */
 	movl	%cr0, %eax
@@ -117,10 +116,16 @@
         /* enable cache */
         movl	%cr0, %eax
 	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
-        movl	%eax, %cr0
+	movl	%eax, %cr0
+#endif
 
 	/* Set up stack pointer */
+#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
+	/* leave some space for the struct ehci_debug_info */
+	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
+#else
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+#endif
 	movl	%eax, %esp
 
 	/* Restore the BIST result */
Index: src/cpu/intel/model_6fx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram.inc	(revision 4842)
+++ src/cpu/intel/model_6fx/cache_as_ram.inc	(working copy)
@@ -101,7 +101,6 @@
 	//movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl
-#endif
 
 	/* Enable Cache As RAM mode by disabling cache */
 	movl	%cr0, %eax
@@ -124,10 +123,16 @@
         /* enable cache */
         movl	%cr0, %eax
 	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
-        movl	%eax, %cr0
+	movl	%eax, %cr0
+#endif
 
 	/* Set up stack pointer */
+#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
+	/* leave some space for the struct ehci_debug_info */
+	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
+#else
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+#endif
 	movl	%eax, %esp
 
 	/* Restore the BIST result */