Patchwork Intel P35/Q35/G33/Q33/G31/P31

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Submitter Loïc Grenié
Date 2009-11-01 20:24:09
Message ID <9b06e8d20911011224y63158971uacf5654a7bb59a68@mail.gmail.com>
Download mbox | patch
Permalink /patch/526/
State Accepted
Headers show

Comments

Loïc Grenié - 2009-11-01 20:24:09
Sorry for the forgotten patch !

  Here is a patch for inteltool to print the registers values
 for the P31..Q35 chipset. The registers are (as far as I
 can tell) unchanged with respect to those of the PM965.
 I've no strong ideas on the names: I've chosen
 PCI_DEVICE_ID_INTEL_82G33 as Northbridge name, it
 can obviously be changed to anything else. I've given
 "P35/Q35/G33/Q33/G31/P31" as description, it can also
 be freely changed.

   Please consider for applying,

         Thanks,

                 Loïc
Paul Menzel - 2009-11-01 21:09:58
Am Sonntag, den 01.11.2009, 21:24 +0100 schrieb Loïc Grenié:

[…]

>    Please consider for applying,

One more thing. Could you add your Signed-off-by line as explained in
the Sign-off Procedure [1]. So that the developers can acknowledge and
commit your patch.


Thanks,

Paul


[1] http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure

Patch

Index: inteltool.h
===================================================================
--- inteltool.h	(revision 4887)
+++ inteltool.h	(working copy)
@@ -52,6 +52,7 @@ 
 #define PCI_DEVICE_ID_INTEL_82945GM		0x27a0
 #define PCI_DEVICE_ID_INTEL_PM965		0x2a00
 #define PCI_DEVICE_ID_INTEL_82975X		0x277c
+#define PCI_DEVICE_ID_INTEL_82G33		0x29c0
 #define PCI_DEVICE_ID_INTEL_X58			0x3405
 
 #define PCI_DEVICE_ID_INTEL_82443LX		0x7180
Index: pcie.c
===================================================================
--- pcie.c	(revision 4887)
+++ pcie.c	(working copy)
@@ -39,6 +39,7 @@ 
 		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
 		break;
  	case PCI_DEVICE_ID_INTEL_PM965:
+ 	case PCI_DEVICE_ID_INTEL_82G33:
  		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
  		epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
  		break;
@@ -86,6 +87,7 @@ 
 		dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
 		break;
  	case PCI_DEVICE_ID_INTEL_PM965:
+ 	case PCI_DEVICE_ID_INTEL_82G33:
  		dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
  		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
  		break;
@@ -135,6 +137,7 @@ 
 		pciexbar_reg = pci_read_long(nb, 0x48);
 		break;
  	case PCI_DEVICE_ID_INTEL_PM965:
+ 	case PCI_DEVICE_ID_INTEL_82G33:
  		pciexbar_reg = pci_read_long(nb, 0x60);
  		pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
  		break;
Index: memory.c
===================================================================
--- memory.c	(revision 4887)
+++ memory.c	(working copy)
@@ -40,6 +40,7 @@ 
 		mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
 		break;
  	case PCI_DEVICE_ID_INTEL_PM965:
+ 	case PCI_DEVICE_ID_INTEL_82G33:
  		mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
  		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
  		break;
Index: inteltool.c
===================================================================
--- inteltool.c	(revision 4887)
+++ inteltool.c	(working copy)
@@ -39,6 +39,7 @@ 
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/Q35/G33/Q33/G31/P31" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },