| Submitter | Magnus Christensson |
|---|---|
| Date | 2009-11-03 15:31:32 |
| Message ID | <4AF04CD4.1030007@virtutech.com> |
| Download | mbox | patch |
| Permalink | /patch/532/ |
| State | Not Applicable |
| Headers | show |
Comments
On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote: > I'm attaching patches for seabios to make it work on the Virtutech > Simics x86-440bx model. Please let me know if there is some other list > that is preferred for seabios patches. > > Patches 1-6 and 9 are not really related to the Virtutech model at all, > so those would be prime candidates to be included in the mainline > version. Thanks Magnus. Gleb I'm not sure if you're on the coreboot mailing list - can you take a look at these patches as well? A URL is at: http://permalink.gmane.org/gmane.linux.bios/55487 -Kevin
On Tue, Nov 03, 2009 at 10:30:12PM -0500, Kevin O'Connor wrote: > On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote: > > I'm attaching patches for seabios to make it work on the Virtutech > > Simics x86-440bx model. Please let me know if there is some other list > > that is preferred for seabios patches. > > > > Patches 1-6 and 9 are not really related to the Virtutech model at all, > > so those would be prime candidates to be included in the mainline > > version. > l> Thanks Magnus. > > Gleb I'm not sure if you're on the coreboot mailing list - can you > take a look at these patches as well? A URL is at: > > http://permalink.gmane.org/gmane.linux.bios/55487 > Can I get them in a mbox format somewhere? Want to tested them to be sure. From review: 1: OK 2: What is the reason for this? x86info --mptable on my 4 core AMD shows MP Table: # APIC ID Version State Family Model Step Flags # 0 0x10 BSP, usable 16 4 1 0x178bfbff # 1 0x10 AP, usable 16 4 1 0x178bfbff # 2 0x10 AP, usable 16 4 1 0x178bfbff # 3 0x10 AP, usable 16 4 1 0x178bfbff 3: And why is this? My mptable spec (from 1997) says that apic id is 8 bit and x86info --mptable on my Intel with 16 logical cpus shows: MP Table: # APIC ID Version State Family Model Step Flags # 0 0x15 BSP, usable 6 10 5 0x0381 # 16 0x15 AP, usable 6 10 5 0x0381 Interesting that on Intel only one entry per physical package. 4: I am not sure why we want to make it faster (waiting anyway) but OK. 5: OK. Wanted to add this by myself for a long time. We configure LINT0 inside KVM now, but this is BIOS job. 6: OK. 7: Don't like VIRTUTECH_IRQ0_OVERRIDE checking inside qemu_cfg_irq0_override(). What about creating irq0_override() in generic code that will call qemu_cfg_irq0_override() if needed. Setting VIRTUTECH_IRQ0_OVERRIDE to 1 by default is not a welcomed too :) 8: Do not set VIRTUTECH_PC_SHADOW to 1 by default please. Otherwise the code is not used by qemu so OK. 9: OK 10: USE_CMOS_BIOS_SMP_COUNT default to 1 -- Gleb.
Patch
From eedd6f2f7378a03f95a7a31968c42940e363049f Mon Sep 17 00:00:00 2001 From: Magnus Christensson <mch@virtutech.com> Date: Tue, 3 Nov 2009 14:46:52 +0100 Subject: [PATCH 10/10] Add USE_CMOS_BIOS_SMP_COUNT option. If disabled, we wait 10ms instead of relying on the cpu count stored in memory. --- src/config.h | 1 + src/smp.c | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/config.h b/src/config.h index 754559b..a9e79cb 100644 --- a/src/config.h +++ b/src/config.h @@ -192,5 +192,6 @@ /* Options for running on the Virtutech Simics x86-440bx machine model */ #define VIRTUTECH_IRQ0_OVERRIDE 1 #define VIRTUTECH_PC_SHADOW 1 +#define USE_CMOS_BIOS_SMP_COUNT 0 #endif // config.h diff --git a/src/smp.c b/src/smp.c index b0852f8..caec5f1 100644 --- a/src/smp.c +++ b/src/smp.c @@ -105,7 +105,7 @@ smp_probe(void) writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector); // Wait for other CPUs to process the SIPI. - if (CONFIG_COREBOOT) { + if (CONFIG_COREBOOT || !USE_CMOS_BIOS_SMP_COUNT) { msleep(10); } else { u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT); -- 1.6.2.5