Patchwork [v2] r4925 makes my linux hang

login
register
about
Submitter Bao, Zheng
Date 2009-11-09 09:01:36
Message ID <DD1CC71B621B004FA76856E5129D6B17032F3B29@sbjgexmb1.amd.com>
Download mbox | patch
Permalink /patch/547/
State Accepted, archived
Headers show

Comments

Bao, Zheng - 2009-11-09 09:01:36
R4925 makes my linux hang. Output is attached.
My board is K8+rs780+sb700, which is close to dbm690t(k8+rs690+sb700).
But dbm690t works well. I don't know why.

Zheng


-----Original Message-----
From: coreboot-bounces@coreboot.org
[mailto:coreboot-bounces@coreboot.org] On Behalf Of svn@coreboot.org
Sent: Saturday, November 07, 2009 7:42 AM
To: coreboot@coreboot.org
Subject: [coreboot] [v2] r4925 - in trunk/src: devices
driversinclude/device mainboard/amd/dbm690t
mainboard/amd/pistachiomainboard/arima/hdama
mainboard/artecgroup/dbe61/realmodemainboard/asi/mb_5blmp
mainboard/asus/mew-vmmainboard/broadcom/blast mainboard/digita

Author: myles
Date: 2009-11-06 23:42:26 +0000 (Fri, 06 Nov 2009)
New Revision: 4925

Removed:
   trunk/src/drivers/pci/
Modified:
   trunk/src/devices/pci_device.c
   trunk/src/devices/pci_rom.c
   trunk/src/drivers/Makefile.inc
   trunk/src/include/device/device.h
   trunk/src/mainboard/amd/dbm690t/Config.lb
   trunk/src/mainboard/amd/dbm690t/devicetree.cb
   trunk/src/mainboard/amd/pistachio/Config.lb
   trunk/src/mainboard/amd/pistachio/devicetree.cb
   trunk/src/mainboard/arima/hdama/Config.lb
   trunk/src/mainboard/arima/hdama/devicetree.cb
   trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
   trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
   trunk/src/mainboard/asi/mb_5blmp/Config.lb
   trunk/src/mainboard/asi/mb_5blmp/devicetree.cb
   trunk/src/mainboard/asus/mew-vm/Config.lb
   trunk/src/mainboard/asus/mew-vm/devicetree.cb
   trunk/src/mainboard/broadcom/blast/Config.lb
   trunk/src/mainboard/broadcom/blast/devicetree.cb
   trunk/src/mainboard/digitallogic/msm586seg/Config.lb
   trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
   trunk/src/mainboard/emulation/qemu-x86/mainboard.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
   trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
   trunk/src/mainboard/hp/dl145_g3/Config.lb
   trunk/src/mainboard/hp/dl145_g3/devicetree.cb
   trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb
   trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
   trunk/src/mainboard/ibm/e326/Config.lb
   trunk/src/mainboard/ibm/e326/devicetree.cb
   trunk/src/mainboard/intel/d945gclf/Config.lb
   trunk/src/mainboard/intel/d945gclf/devicetree.cb
   trunk/src/mainboard/intel/xe7501devkit/Config.lb
   trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
   trunk/src/mainboard/iwill/dk8_htx/Config.lb
   trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
   trunk/src/mainboard/kontron/986lcd-m/Config.lb
   trunk/src/mainboard/kontron/986lcd-m/devicetree.cb
   trunk/src/mainboard/kontron/kt690/Config.lb
   trunk/src/mainboard/kontron/kt690/devicetree.cb
   trunk/src/mainboard/mitac/6513wu/Config.lb
   trunk/src/mainboard/mitac/6513wu/devicetree.cb
   trunk/src/mainboard/msi/ms6178/Config.lb
   trunk/src/mainboard/msi/ms6178/devicetree.cb
   trunk/src/mainboard/msi/ms9185/Config.lb
   trunk/src/mainboard/msi/ms9185/devicetree.cb
   trunk/src/mainboard/msi/ms9282/Config.lb
   trunk/src/mainboard/msi/ms9282/devicetree.cb
   trunk/src/mainboard/nec/powermate2000/Config.lb
   trunk/src/mainboard/nec/powermate2000/devicetree.cb
   trunk/src/mainboard/newisys/khepri/Config.lb
   trunk/src/mainboard/rca/rm4100/Config.lb
   trunk/src/mainboard/rca/rm4100/devicetree.cb
   trunk/src/mainboard/sunw/ultra40/Config.lb
   trunk/src/mainboard/sunw/ultra40/devicetree.cb
   trunk/src/mainboard/supermicro/h8dme/Config.lb
   trunk/src/mainboard/supermicro/h8dme/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr/Config.lb
   trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
   trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
   trunk/src/mainboard/technexion/tim5690/Config.lb
   trunk/src/mainboard/technexion/tim5690/devicetree.cb
   trunk/src/mainboard/technexion/tim8690/Config.lb
   trunk/src/mainboard/technexion/tim8690/devicetree.cb
   trunk/src/mainboard/technologic/ts5300/Config.lb
   trunk/src/mainboard/technologic/ts5300/devicetree.cb
   trunk/src/mainboard/thomson/ip1000/Config.lb
   trunk/src/mainboard/thomson/ip1000/devicetree.cb
   trunk/src/mainboard/tyan/s2735/Config.lb
   trunk/src/mainboard/tyan/s2735/devicetree.cb
   trunk/src/mainboard/tyan/s2850/Config.lb
   trunk/src/mainboard/tyan/s2850/devicetree.cb
   trunk/src/mainboard/tyan/s2875/Config.lb
   trunk/src/mainboard/tyan/s2875/devicetree.cb
   trunk/src/mainboard/tyan/s2880/Config.lb
   trunk/src/mainboard/tyan/s2880/devicetree.cb
   trunk/src/mainboard/tyan/s2881/Config.lb
   trunk/src/mainboard/tyan/s2881/devicetree.cb
   trunk/src/mainboard/tyan/s2882/Config.lb
   trunk/src/mainboard/tyan/s2882/devicetree.cb
   trunk/src/mainboard/tyan/s2885/Config.lb
   trunk/src/mainboard/tyan/s2885/devicetree.cb
   trunk/src/mainboard/tyan/s2891/devicetree.cb
   trunk/src/mainboard/tyan/s2892/devicetree.cb
   trunk/src/mainboard/tyan/s2895/devicetree.cb
   trunk/src/mainboard/tyan/s2912_fam10/Config.lb
   trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
   trunk/src/mainboard/tyan/s4880/Config.lb
   trunk/src/mainboard/tyan/s4880/devicetree.cb
   trunk/src/mainboard/tyan/s4882/Config.lb
   trunk/src/mainboard/tyan/s4882/devicetree.cb
   trunk/src/mainboard/via/epia/Config.lb
   trunk/src/mainboard/via/epia/devicetree.cb
   trunk/src/mainboard/via/vt8454c/Config.lb
   trunk/src/mainboard/via/vt8454c/devicetree.cb
   trunk/src/northbridge/via/cn400/vga.c
   trunk/src/northbridge/via/cn700/vga.c
   trunk/src/northbridge/via/cx700/cx700_vga.c
   trunk/src/northbridge/via/vt8623/northbridge.c
   trunk/src/northbridge/via/vx800/vga.c
   trunk/src/southbridge/nvidia/ck804/chip.h
   trunk/src/southbridge/nvidia/ck804/ck804.c
Log:
Remove drivers/pci/onboard.  The only purpose was for option ROMs, which
are
now handled more generically using CBFS.

Simplify the option ROM code in device/pci_rom.c, since there are only
two ways
to get a ROM address now (CBFS and the device) and add an exception for
qemu.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


Modified: trunk/src/devices/pci_device.c
===================================================================
--- trunk/src/devices/pci_device.c	2009-11-06 17:32:32 UTC (rev
4924)
+++ trunk/src/devices/pci_device.c	2009-11-06 23:42:26 UTC (rev
4925)
@@ -285,11 +285,6 @@
 	unsigned long value;
 	resource_t moving;
 
-	if ((dev->on_mainboard) && (dev->rom_address == 0)) {
-		/* Skip it if rom_address is not set in the MB
Config.lb. */
-		return;
-	}
-
 	/* Initialize the resources to nothing. */
 	resource = new_resource(dev, index);
 
@@ -326,18 +321,6 @@
 		}
 		resource->flags = 0;
 	}
-
-	/* For on board device with embedded ROM image, the ROM image is
at
-	 * fixed address specified in the Config.lb, the
dev->rom_address is
-	 * inited by driver_pci_onboard_ops::enable_dev() */
-	if ((dev->on_mainboard) && (dev->rom_address != 0)) {
-		resource->base = dev->rom_address;
-		/* The resource allocator needs the size to be non-zero.
*/
-		resource->size = 0x100;
-		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY
|
-		    IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-	}
-
 	compact_resources(dev);
 }
 

Modified: trunk/src/devices/pci_rom.c
+		rom_header = (struct rom_header *)rom_address;
 	}
 
-	rom_header = (struct rom_header *)rom_address;
 	printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size
0x%04x, data ptr 0x%04x\n",
 		    le32_to_cpu(rom_header->signature),
 		    rom_header->size * 512,
le32_to_cpu(rom_header->data));
@@ -76,11 +71,12 @@
 		return NULL;
 	}
 
-	rom_data = (struct pci_data *) ((void *)rom_header +
le32_to_cpu(rom_header->data));
+	rom_data = (((void *)rom_header) +
le32_to_cpu(rom_header->data));
+
 	printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n",
 		    rom_data->vendor, rom_data->device);
 	if (dev->vendor != rom_data->vendor || dev->device !=
rom_data->device) {
-		printk_err("Device or Vendor ID mismatch Vendor %04x,
Device %04x\n",
+		printk_err("ID mismatch: Vendor ID %04x, Device ID
%04x\n",
 			   rom_data->vendor, rom_data->device);
 		return NULL;
 	}
@@ -90,7 +86,8 @@
 		    rom_data->type);
 	if (dev->class != ((rom_data->class_hi << 8) |
rom_data->class_lo)) {
 		printk_debug("Class Code mismatch ROM %08x, dev %08x\n",

-			    (rom_data->class_hi << 8) |
rom_data->class_lo, dev->class);
+			     (rom_data->class_hi << 8) |
rom_data->class_lo,
+			     dev->class);
 		//return NULL;
 	}
 

Modified: trunk/src/drivers/Makefile.inc
===================================================================
--- trunk/src/drivers/Makefile.inc	2009-11-06 17:32:32 UTC (rev
4924)
+++ trunk/src/drivers/Makefile.inc	2009-11-06 23:42:26 UTC (rev
4925)
@@ -1,3 +1,2 @@
-subdirs-y += pci
 subdirs-y += generic/debug
 subdirs-y += ati/ragexl

Modified: trunk/src/include/device/device.h
===================================================================
--- trunk/src/include/device/device.h	2009-11-06 17:32:32 UTC (rev
4924)
+++ trunk/src/include/device/device.h	2009-11-06 23:42:26 UTC (rev
4925)
@@ -70,7 +70,6 @@
 	unsigned int    enabled : 1;	/* set if we should enable the
device */
 	unsigned int    initialized : 1; /* set if we have initialized
the device */
 	unsigned int    on_mainboard : 1;
-	unsigned long   rom_address;
 
 	u8 command;
 

Modified: trunk/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb
===================================================================
--- trunk/src/mainboard/amd/dbm690t/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/amd/dbm690t/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/amd/pistachio/Config.lb
===================================================================
--- trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -156,9 +156,7 @@
 					device pci 0.0 on end # HT
0x7910
 				#	device pci 0.1 off end # CLK
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb
===================================================================
--- trunk/src/mainboard/amd/pistachio/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/amd/pistachio/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -21,9 +21,7 @@
 					device pci 0.0 on end # HT
0x7910
 				#	device pci 0.1 off end # CLK
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/arima/hdama/Config.lb
===================================================================
--- trunk/src/mainboard/arima/hdama/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/arima/hdama/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -177,9 +177,7 @@
 						device pci 0.1 on  end
# USB1
 						device pci 0.2 off end
# USB 2.0
 						device pci 1.0 off end
# LAN
-						chip drivers/pci/onboard
-							device pci 6.0
on end # ATI Rage XL
-						end
+						device pci 6.0 on end #
ATI Rage XL
 						## PCI Slot 5 (correct?)
 						#chip
drivers/generic/generic
 						#	device pci 5.0
on

Modified: trunk/src/mainboard/arima/hdama/devicetree.cb
===================================================================
--- trunk/src/mainboard/arima/hdama/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/arima/hdama/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -73,9 +73,7 @@
 						device pci 0.1 on  end
# USB1
 						device pci 0.2 off end
# USB 2.0
 						device pci 1.0 off end
# LAN
-						chip drivers/pci/onboard
-							device pci 6.0
on end # ATI Rage XL
-						end
+						device pci 6.0 on end #
ATI Rage XL
 						## PCI Slot 5 (correct?)
 						#chip
drivers/generic/generic
 						#	device pci 5.0
on

Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
===================================================================
--- trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
2009-11-06 23:42:26 UTC (rev 4925)
@@ -1,10 +1,6 @@
 #ifndef PCI_REALMODE_H
 #define PCI_REALMODE_H
 
-struct drivers_pci_realmode_config 
-{
-       unsigned long rom_address;
-};
 //struct chip_operations;
 extern struct chip_operations drivers_pci_realmode_ops;
 

Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
===================================================================
--- trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
2009-11-06 23:42:26 UTC (rev 4925)
@@ -74,36 +74,6 @@
   emulator to successfully run this bios.
 */
 
-
-
-
-/*
-  Modified to be an universal driver for loading VGA ROMs.
-  Aug 2006, anti.sullin@artecdesign.ee, Artec Design
-  
-  USAGE:
-  	define in your motherboard Config.lb file in device hierarchy 
-  	around the VGA pci device realmode chip and define its rom
address.
-	Rom address is read from Config.lb, this rom is then copied to
0xC000 and then excecuted
-  	
-  		chip drivers/pci/realmode
-				device pci 1.1 on end
# VGA
-				register "rom_address" = "0xfffc0000"
# at the beginning of 256k
-		end
-  	
-  	then, chip enable is called at this list first traversal, and
this sets
-  	up device's init callback. Device init is called during last
list traversal and
-  	so, other hw should be already initialized to run vga bios
successfully.
-*/
-
-
-
-
-
-
-
-
-
 /* Declare a temporary global descriptor table - necessary because the
    Core part of the bios no longer sets up any 16 bit segments */
 __asm__ (
@@ -918,8 +888,6 @@
 
 	// code to make vga init go through the emulator - as of yet
this does not workfor the epia-m
 	dev->on_mainboard=1;
-	dev->rom_address = (void *)cfg->rom_address;
-
 	pci_dev_init(dev);
 
 	// code to make vga init run in real mode - does work but
against the current coreboot philosophy 

Modified: trunk/src/mainboard/asi/mb_5blmp/Config.lb
===================================================================
--- trunk/src/mainboard/asi/mb_5blmp/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/asi/mb_5blmp/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -135,11 +135,6 @@
       device pci 12.2 on  end		# IDE
       device pci 12.3 on  end		# Audio
       device pci 12.4 on  end		# VGA (onboard)
-      # device pci 12.4 on		# VGA (onboard)
-      #   chip drivers/pci/onboard
-      #     device pci 12.4 on end
-      #   end
-      # end
       device pci 13.0 on end		# USB
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/asi/mb_5blmp/devicetree.cb
===================================================================
--- trunk/src/mainboard/asi/mb_5blmp/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/asi/mb_5blmp/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -37,11 +37,6 @@
       device pci 12.2 on  end		# IDE
       device pci 12.3 on  end		# Audio
       device pci 12.4 on  end		# VGA (onboard)
-      # device pci 12.4 on		# VGA (onboard)
-      #   chip drivers/pci/onboard
-      #     device pci 12.4 on end
-      #   end
-      # end
       device pci 13.0 on end		# USB
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/asus/mew-vm/Config.lb
===================================================================
--- trunk/src/mainboard/asus/mew-vm/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/asus/mew-vm/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -97,18 +97,14 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end # Host bridge
 		device pci 1.0 on # Onboard Video
-			#chip drivers/pci/onboard
 			#	device pci 1.0 on end
-		        #end
 		end
 		chip southbridge/intel/i82801xx # Southbridge
       			register "ide0_enable" = "1"
       			register "ide1_enable" = "1"
 
 			device pci 1e.0 on # PCI Bridge
-				#chip drivers/pci/onboard
 				#	device pci 1.0 on end
-			        #end
 			end
 			device pci 1f.0 on  # ISA/LPC? Bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/asus/mew-vm/devicetree.cb
===================================================================
--- trunk/src/mainboard/asus/mew-vm/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/asus/mew-vm/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -2,18 +2,14 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end # Host bridge
 		device pci 1.0 on # Onboard Video
-			#chip drivers/pci/onboard
 			#	device pci 1.0 on end
-		        #end
 		end
 		chip southbridge/intel/i82801xx # Southbridge
       			register "ide0_enable" = "1"
       			register "ide1_enable" = "1"
 
 			device pci 1e.0 on # PCI Bridge
-				#chip drivers/pci/onboard
 				#	device pci 1.0 on end
-			        #end
 			end
 			device pci 1f.0 on  # ISA/LPC? Bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/broadcom/blast/Config.lb
===================================================================
--- trunk/src/mainboard/broadcom/blast/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/broadcom/blast/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -207,21 +207,8 @@
                                         device pci 2.0 on end # USB
0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE
(6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 4.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed, fake one to get the rom_address
-                                                                    #
if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if
CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
-                                        end
+                                        device pci 4.0 on end # it is
in bcm5785_0 bus
                                 end
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end #
fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 5.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed
-#                                        end
-
-
 			end #  device pci 18.0
 
                         device pci 18.0 on end

Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb
===================================================================
--- trunk/src/mainboard/broadcom/blast/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/broadcom/blast/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -105,21 +105,8 @@
                                         device pci 2.0 on end # USB
0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE
(6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 4.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed, fake one to get the rom_address
-                                                                    #
if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if
CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
-                                        end
+                                        device pci 4.0 on end # it is
in bcm5785_0 bus
                                 end
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end #
fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 5.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed
-#                                        end
-
-
 			end #  device pci 18.0
 
                         device pci 18.0 on end

Modified: trunk/src/mainboard/digitallogic/msm586seg/Config.lb
===================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/Config.lb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/digitallogic/msm586seg/Config.lb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -102,13 +102,8 @@
 chip cpu/amd/sc520
 	device pci_domain 0 on 
 		device pci 0.0 on end
-	
-		chip drivers/pci/onboard
-			device pci 12.0 on end # enet
-		end
-		chip drivers/pci/onboard
-			device pci 14.0 on end # 69000
-		end
+		device pci 12.0 on end # enet
+		device pci 14.0 on end # 69000
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
===================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -1,13 +1,8 @@
 chip cpu/amd/sc520
 	device pci_domain 0 on 
 		device pci 0.0 on end
-	
-		chip drivers/pci/onboard
-			device pci 12.0 on end # enet
-		end
-		chip drivers/pci/onboard
-			device pci 14.0 on end # 69000
-		end
+		device pci 12.0 on end # enet
+		device pci 14.0 on end # 69000
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/emulation/qemu-x86/mainboard.c
===================================================================
--- trunk/src/mainboard/emulation/qemu-x86/mainboard.c	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/emulation/qemu-x86/mainboard.c	2009-11-06
23:42:26 UTC (rev 4925)
@@ -16,7 +16,6 @@
 	 * force coreboot to use it.
 	 */
 	dev->on_mainboard = 1;
-	dev->rom_address = 0xc0000;
 
 	/* Now do the usual initialization */
 	pci_dev_init(dev);

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -178,9 +178,7 @@
 			        chip southbridge/sis/sis966
 					device pci 0.0 on end   #
Northbridge
 					device pci 1.0 on
# AGP bridge
-					  chip drivers/pci/onboard
# Integrated VGA
 						device pci 0.0 on end
-					  end
 					end
                 			device pci 2.0 on # LPC
 						chip superio/ite/it8716f

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -11,9 +11,7 @@
 			        chip southbridge/sis/sis966
 					device pci 0.0 on end   #
Northbridge
 					device pci 1.0 on
# AGP bridge
-					  chip drivers/pci/onboard
# Integrated VGA
 						device pci 0.0 on end
-					  end
 					end
                 			device pci 2.0 on # LPC
 						chip superio/ite/it8716f

Modified: trunk/src/mainboard/hp/dl145_g3/Config.lb
===================================================================
--- trunk/src/mainboard/hp/dl145_g3/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/hp/dl145_g3/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -195,15 +195,6 @@
 					device pci 2.1 on end # USB
 					device pci 2.2 on end # USB
 					device pci 3.0 on end # VGA
-					
-					#bx_a013+ start
-					#chip drivers/pci/onboard
#SATA2
-					#	device pci 5.0 on end
-					#	device pci 5.1 on end
-					#	device pci 5.2 on end
-					#	device pci 5.3 on end
-					#end
-					#bx_a013+ end
 				end
 			end
 			device pci 18.0 on end

Modified: trunk/src/mainboard/hp/dl145_g3/devicetree.cb
===================================================================
--- trunk/src/mainboard/hp/dl145_g3/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/dl145_g3/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -72,15 +72,6 @@
 					device pci 2.1 on end # USB
 					device pci 2.2 on end # USB
 					device pci 3.0 on end # VGA
-					
-					#bx_a013+ start
-					#chip drivers/pci/onboard
#SATA2
-					#	device pci 5.0 on end
-					#	device pci 5.1 on end
-					#	device pci 5.2 on end
-					#	device pci 5.3 on end
-					#end
-					#bx_a013+ end
 				end
 			end
 			device pci 18.0 on end

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb
===================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -76,9 +76,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
===================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -7,9 +7,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/ibm/e326/Config.lb
===================================================================
--- trunk/src/mainboard/ibm/e326/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/ibm/e326/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -125,9 +125,7 @@
 						device pci 0.1 on end
 						device pci 0.2 on end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end # ATI Rage XL
-                                                end
+                                               device pci 5.0 on end #
ATI Rage XL
 					end
 					device pci 1.0 on
 						chip superio/nsc/pc87366

Modified: trunk/src/mainboard/ibm/e326/devicetree.cb
===================================================================
--- trunk/src/mainboard/ibm/e326/devicetree.cb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/ibm/e326/devicetree.cb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -21,9 +21,7 @@
 						device pci 0.1 on end
 						device pci 0.2 on end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end # ATI Rage XL
-                                                end
+                                               device pci 5.0 on end #
ATI Rage XL
 					end
 					device pci 1.0 on
 						chip superio/nsc/pc87366

Modified: trunk/src/mainboard/intel/d945gclf/Config.lb
===================================================================
--- trunk/src/mainboard/intel/d945gclf/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/d945gclf/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -150,9 +150,7 @@
         device pci_domain 0 on 
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb
===================================================================
--- trunk/src/mainboard/intel/d945gclf/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/d945gclf/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -28,9 +28,7 @@
         device pci_domain 0 on 
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/intel/xe7501devkit/Config.lb
===================================================================
--- trunk/src/mainboard/intel/xe7501devkit/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/xe7501devkit/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -127,9 +127,7 @@
 			device pci 1d.1 off end # USB (not populated)
 			device pci 1d.2 off end # USB (not populated)
 			device pci 1e.0 on # Hub to PCI bridge
-				chip drivers/pci/onboard # VGA ROM
-					device pci 0.0 on end
-				end
+				device pci 0.0 on end
 			end
 			device pci 1f.0 on # LPC bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
===================================================================
--- trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -25,9 +25,7 @@
 			device pci 1d.1 off end # USB (not populated)
 			device pci 1d.2 off end # USB (not populated)
 			device pci 1e.0 on # Hub to PCI bridge
-				chip drivers/pci/onboard # VGA ROM
-					device pci 0.0 on end
-				end
+				device pci 0.0 on end
 			end
 			device pci 1f.0 on # LPC bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/iwill/dk8_htx/Config.lb
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/iwill/dk8_htx/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -232,9 +232,6 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                #chip
drivers/pci/onboard
-                                                #        device pci 6.0
on end
-                                                #end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -24,9 +24,6 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                #chip
drivers/pci/onboard
-                                                #        device pci 6.0
on end
-                                                #end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/kontron/986lcd-m/Config.lb
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/986lcd-m/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -153,9 +153,7 @@
                 device pci 00.0 on end # host bridge
 		# autodetect 0:1.0 because it might or might not be
there.
 		# device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/kontron/986lcd-m/devicetree.cb
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/986lcd-m/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -9,9 +9,7 @@
         device pci_domain 0 on 
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/kontron/kt690/Config.lb
===================================================================
--- trunk/src/mainboard/kontron/kt690/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/kontron/kt690/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb
===================================================================
--- trunk/src/mainboard/kontron/kt690/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/kt690/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/mitac/6513wu/Config.lb
===================================================================
--- trunk/src/mainboard/mitac/6513wu/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/mitac/6513wu/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -80,9 +80,7 @@
   end
   device pci_domain 0 on                # PCI domain
     device pci 0.0 on end               # Graphics Memory Controller
Hub (GMCH)
-    chip drivers/pci/onboard
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end
     chip southbridge/intel/i82801xx     # Southbridge
       register "pirqa_routing" = "0x03"
       register "pirqb_routing" = "0x05"

Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb
===================================================================
--- trunk/src/mainboard/mitac/6513wu/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/mitac/6513wu/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -26,9 +26,7 @@
   end
   device pci_domain 0 on                # PCI domain
     device pci 0.0 on end               # Graphics Memory Controller
Hub (GMCH)
-    chip drivers/pci/onboard
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end
     chip southbridge/intel/i82801xx     # Southbridge
       register "pirqa_routing" = "0x03"
       register "pirqb_routing" = "0x05"

Modified: trunk/src/mainboard/msi/ms6178/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms6178/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/msi/ms6178/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -75,9 +75,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms6178/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms6178/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -26,9 +26,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/msi/ms9185/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms9185/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/msi/ms9185/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -207,29 +207,8 @@
                                         device pci 2.0 on end # USB
0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE
(6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 3.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed, fake one to get the rom_address
-                                                                    #
if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if
CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
-                                        end
-                                       #bx_a013+ start
-                                       #chip drivers/pci/onboard
#SATA2
-                                       #       device pci 5.0 on end
-                                       #       device pci 5.1 on end
-                                       #       device pci 5.2 on end
-                                       #       device pci 5.3 on end
-                                       #end
-                                       #bx_a013+ end
-
+                                        device pci 3.0 on end # it is
in bcm5785_0 bus
                                 end
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end #
fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 4.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed
-#                                        end
-
                        end #  device pci 18.0
                        device pci 18.1 on end
                        device pci 18.2 on end

Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms9185/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms9185/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -73,29 +73,8 @@
                                         device pci 2.0 on end # USB
0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE
(6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 3.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed, fake one to get the rom_address
-                                                                    #
if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if
CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
-                                        end
-                                       #bx_a013+ start
-                                       #chip drivers/pci/onboard
#SATA2
-                                       #       device pci 5.0 on end
-                                       #       device pci 5.1 on end
-                                       #       device pci 5.2 on end
-                                       #       device pci 5.3 on end
-                                       #end
-                                       #bx_a013+ end
-
+                                        device pci 3.0 on end # it is
in bcm5785_0 bus
                                 end
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end #
fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 4.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed
-#                                        end
-
                        end #  device pci 18.0
                        device pci 18.1 on end
                        device pci 18.2 on end

Modified: trunk/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms9282/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/msi/ms9282/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -278,27 +278,21 @@
                                        device pci 5.1 on  end # SATA 1
                                        device pci 5.2 on  end # SATA 2
                                        device pci 6.0 on  #P2P
-                                               chip drivers/pci/onboard
-                                                       device pci 4.0
on end
-                                               end
+                                               device pci 4.0 on end
                                        end # P2P
                                        device pci 7.0 on end # reserve
                                        device pci 8.0 on end # MAC0
                                        device pci 9.0 on end # MAC1
                                        device pci a.0 on
                                                device pci 0.0 on
-                                                       chip
drivers/pci/onboard
-                                                               device
pci 4.0 on end  #pci_E lan1
-                                                               device
pci 4.1 on end  #pci_E lan2
-                                                       end
+                                                       device pci 4.0
on end  #pci_E lan1
+                                                       device pci 4.1
on end  #pci_E lan2
                                                end
                                        end # 0x376
                                                device pci b.0 on  end #
PCI E 0x374
                                        device pci c.0 on  end
                                        device pci d.0 on   #SAS
-                                               chip drivers/pci/onboard
-                                                       device pci 0.0
on end
-                                               end
+                                               device pci 0.0 on end
                                        end # PCI E 1 0x378
                                        device pci e.0 on end # PCI E 0
0x375
                                        device pci f.0 on end   #PCI E
0x377  pci_E slot

Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms9282/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms9282/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -137,27 +137,21 @@
                                        device pci 5.1 on  end # SATA 1
                                        device pci 5.2 on  end # SATA 2
                                        device pci 6.0 on  #P2P
-                                               chip drivers/pci/onboard
-                                                       device pci 4.0
on end
-                                               end
+                                               device pci 4.0 on end
                                        end # P2P
                                        device pci 7.0 on end # reserve
                                        device pci 8.0 on end # MAC0
                                        device pci 9.0 on end # MAC1
                                        device pci a.0 on
                                                device pci 0.0 on
-                                                       chip
drivers/pci/onboard
-                                                               device
pci 4.0 on end  #pci_E lan1
-                                                               device
pci 4.1 on end  #pci_E lan2
-                                                       end
+                                                       device pci 4.0
on end  #pci_E lan1
+                                                       device pci 4.1
on end  #pci_E lan2
                                                end
                                        end # 0x376
                                                device pci b.0 on  end #
PCI E 0x374
                                        device pci c.0 on  end
                                        device pci d.0 on   #SAS
-                                               chip drivers/pci/onboard
-                                                       device pci 0.0
on end
-                                               end
+                                               device pci 0.0 on end
                                        end # PCI E 1 0x378
                                        device pci e.0 on end # PCI E 0
0x375
                                        device pci f.0 on end   #PCI E
0x377  pci_E slot

Modified: trunk/src/mainboard/nec/powermate2000/Config.lb
===================================================================
--- trunk/src/mainboard/nec/powermate2000/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/nec/powermate2000/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -75,11 +75,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    device pci 1.0 off				# Onboard video
-      # chip drivers/pci/onboard
-      #   device pci 1.0 on end
-      # end
-    end
+    device pci 1.0 off end			# Onboard video
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb
===================================================================
--- trunk/src/mainboard/nec/powermate2000/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/nec/powermate2000/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -6,11 +6,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    device pci 1.0 off				# Onboard video
-      # chip drivers/pci/onboard
-      #   device pci 1.0 on end
-      # end
-    end
+    device pci 1.0 off end			# Onboard video
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/newisys/khepri/Config.lb
===================================================================
--- trunk/src/mainboard/newisys/khepri/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/newisys/khepri/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -98,8 +98,6 @@
 
 config chip.h
 
-# FIXME: ROM for onboard VGA
-
 chip northbridge/amd/amdk8/root_complex
 	device apic_cluster 0 on
 		chip cpu/amd/socket_940

Modified: trunk/src/mainboard/rca/rm4100/Config.lb
===================================================================
--- trunk/src/mainboard/rca/rm4100/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/rca/rm4100/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -75,9 +75,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb
===================================================================
--- trunk/src/mainboard/rca/rm4100/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/rca/rm4100/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -1,9 +1,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- trunk/src/mainboard/sunw/ultra40/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/sunw/ultra40/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -210,8 +210,6 @@
         	                        register "ide1_enable" = "1"
                 	                register "sata0_enable" = "1"
                         	        register "sata1_enable" = "1"
-#					register "nic_rom_address" =
"0xfff80000" # 64k
-#					register "raid_rom_address" =
"0xfff90000"
 					register "mac_eeprom_smbus" =
"3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" =
"0x51"
 				end
@@ -243,7 +241,6 @@
                                 	device pci c.0 off end # PCI E 2
                                 	device pci d.0 off end # PCI E 1
                                 	device pci e.0 on end # PCI E 0
-#					register "nic_rom_address" =
"0xfff80000" # 64k
                                         register "mac_eeprom_smbus" =
"3"
                                         register "mac_eeprom_addr" =
"0x51"
                         	end

Modified: trunk/src/mainboard/sunw/ultra40/devicetree.cb
===================================================================
--- trunk/src/mainboard/sunw/ultra40/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/sunw/ultra40/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -106,8 +106,6 @@
         	                        register "ide1_enable" = "1"
                 	                register "sata0_enable" = "1"
                         	        register "sata1_enable" = "1"
-#					register "nic_rom_address" =
"0xfff80000" # 64k
-#					register "raid_rom_address" =
"0xfff90000"
 					register "mac_eeprom_smbus" =
"3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" =
"0x51"
 				end
@@ -139,7 +137,6 @@
                                 	device pci c.0 off end # PCI E 2
                                 	device pci d.0 off end # PCI E 1
                                 	device pci e.0 on end # PCI E 0
-#					register "nic_rom_address" =
"0xfff80000" # 64k
                                         register "mac_eeprom_smbus" =
"3"
                                         register "mac_eeprom_addr" =
"0x51"
                         	end

Modified: trunk/src/mainboard/supermicro/h8dme/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dme/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -254,9 +254,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -92,9 +92,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -276,9 +276,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -112,9 +112,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -280,9 +280,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -114,9 +114,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/technexion/tim5690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb
===================================================================
--- trunk/src/mainboard/technexion/tim5690/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim5690/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/technexion/tim8690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb
===================================================================
--- trunk/src/mainboard/technexion/tim8690/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim8690/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/technologic/ts5300/Config.lb
===================================================================
--- trunk/src/mainboard/technologic/ts5300/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technologic/ts5300/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -104,12 +104,6 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end
 	
-#		chip drivers/pci/onboard
-#			device pci 12.0 on end # enet
-#		end
-#		chip drivers/pci/onboard
-#			device pci 14.0 on end # 69000
-#		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/technologic/ts5300/devicetree.cb
===================================================================
--- trunk/src/mainboard/technologic/ts5300/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technologic/ts5300/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -2,12 +2,6 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end
 	
-#		chip drivers/pci/onboard
-#			device pci 12.0 on end # enet
-#		end
-#		chip drivers/pci/onboard
-#			device pci 14.0 on end # 69000
-#		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/thomson/ip1000/Config.lb
===================================================================
--- trunk/src/mainboard/thomson/ip1000/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/thomson/ip1000/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -75,9 +75,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb
===================================================================
--- trunk/src/mainboard/thomson/ip1000/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/thomson/ip1000/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -1,9 +1,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/tyan/s2735/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2735/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2735/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -100,10 +100,8 @@
         		chip southbridge/intel/i82870
         	        	device pci 1c.0 on end
 		                device pci 1d.0 on 
-					chip drivers/pci/onboard
-                                        	device pci 1.0 on end #
intel lan
-                                                device pci 1.1 on end
-                                        end
+                                     	 device pci 1.0 on end # intel
lan
+                                        device pci 1.1 on end
 				end
         	                device pci 1e.0 on end
         	                device pci 1f.0 on end
@@ -117,12 +115,8 @@
         	        device pci 1d.3 on end
 		        device pci 1d.7 on end
 		        device pci 1e.0 on 
-                        	chip drivers/pci/onboard
-                                	device pci 1.0 on end # intel
lan 10/100
-                                end
-                                chip drivers/pci/onboard
-                                        device pci 2.0 on end # ati 
-                                end
+                             	device pci 1.0 on end # intel lan 10/100
+                                device pci 2.0 on end # ati
 			end
 		        device pci 1f.0 on
 				chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2735/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2735/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2735/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -6,10 +6,8 @@
         		chip southbridge/intel/i82870
         	        	device pci 1c.0 on end
 		                device pci 1d.0 on 
-					chip drivers/pci/onboard
-                                        	device pci 1.0 on end #
intel lan
-                                                device pci 1.1 on end
-                                        end
+                                     	 device pci 1.0 on end # intel
lan
+                                        device pci 1.1 on end
 				end
         	                device pci 1e.0 on end
         	                device pci 1f.0 on end
@@ -23,12 +21,8 @@
         	        device pci 1d.3 on end
 		        device pci 1d.7 on end
 		        device pci 1e.0 on 
-                        	chip drivers/pci/onboard
-                                	device pci 1.0 on end # intel
lan 10/100
-                                end
-                                chip drivers/pci/onboard
-                                        device pci 2.0 on end # ati 
-                                end
+                             	device pci 1.0 on end # intel lan 10/100
+                                device pci 2.0 on end # ati
 			end
 		        device pci 1f.0 on
 				chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2850/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2850/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2850/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -119,9 +119,7 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip
drivers/ati/ragexl
-						chip drivers/pci/onboard
-                                                        device pci b.0
on end
-                                                end
+                                                device pci b.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2850/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2850/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -17,9 +17,7 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip
drivers/ati/ragexl
-						chip drivers/pci/onboard
-                                                        device pci b.0
on end
-                                                end
+                                                device pci b.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2875/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2875/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2875/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -123,9 +123,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end
-                                                end
+                                                device pci 5.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2875/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2875/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -21,9 +21,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end
-                                                end
+                                                device pci 5.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2880/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2880/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2880/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -113,10 +113,8 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end #broadcom
-							device pci 9.1
on end 
-                                                end
+                                                device pci 9.0 on end
#broadcom
+						device pci 9.1 on end
 #                                                chip
drivers/lsi/53c1030
 #                                                        device pci a.0
on end
 #                                                        device pci a.1
on end
@@ -135,12 +133,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end #some sata
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end #adti
-                                                end
+                                                device pci 5.0 on end
#some sata
+                                                device pci 6.0 on end
#adti
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2880/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2880/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -11,10 +11,8 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end #broadcom
-							device pci 9.1
on end 
-                                                end
+                                                device pci 9.0 on end
#broadcom
+						device pci 9.1 on end
 #                                                chip
drivers/lsi/53c1030
 #                                                        device pci a.0
on end
 #                                                        device pci a.1
on end
@@ -33,12 +31,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end #some sata
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end #adti
-                                                end
+                                                device pci 5.0 on end
#some sata
+                                                device pci 6.0 on end
#adti
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2881/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2881/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2881/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -115,14 +115,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # Broadcom 5704
-                                                        device pci 9.1
on end
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci a.0
on end # Adaptic
-                                                        device pci a.1
on end
-                                                end
+                                                device pci 9.0 on end #
Broadcom 5704
+                                                device pci 9.1 on end
+                                                device pci a.0 on end #
Adaptic
+                                                device pci a.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -136,12 +132,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end # SiI
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 5.0 on end #
SiI
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2881/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2881/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -13,14 +13,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # Broadcom 5704
-                                                        device pci 9.1
on end
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci a.0
on end # Adaptic
-                                                        device pci a.1
on end
-                                                end
+                                                device pci 9.0 on end #
Broadcom 5704
+                                                device pci 9.1 on end
+                                                device pci a.0 on end #
Adaptic
+                                                device pci a.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -34,12 +30,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end # SiI
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 5.0 on end #
SiI
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2882/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2882/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2882/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -114,14 +114,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on
-                                                chip
drivers/pci/onboard 
-                                                        device pci 6.0
on end # adaptec
-                                                        device pci 6.1
on end
-                                                end 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # broadcom 5704
-                                                        device pci 9.1
on end
-                                                end
+                                                device pci 6.0 on end #
adaptec
+                                                device pci 6.1 on end
+                                                device pci 9.0 on end #
broadcom 5704
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -135,16 +131,11 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard  
-                                                        device pci 5.0
on end
-                                                end
+                                                device pci 5.0 on end
                                         #       chip drivers/ati/ragexl
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
-                                                chip
drivers/pci/onboard 
-                                                        device pci 8.0
on end #intel 10/100
-                                                end
+                                                device pci 6.0 on end
+                                        #       end
+                                                device pci 8.0 on end
#intel 10/100
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2882/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2882/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -12,14 +12,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on
-                                                chip
drivers/pci/onboard 
-                                                        device pci 6.0
on end # adaptec
-                                                        device pci 6.1
on end
-                                                end 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # broadcom 5704
-                                                        device pci 9.1
on end
-                                                end
+                                                device pci 6.0 on end #
adaptec
+                                                device pci 6.1 on end
+                                                device pci 9.0 on end #
broadcom 5704
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -33,16 +29,11 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard  
-                                                        device pci 5.0
on end
-                                                end
+                                                device pci 5.0 on end
                                         #       chip drivers/ati/ragexl
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
-                                                chip
drivers/pci/onboard 
-                                                        device pci 8.0
on end #intel 10/100
-                                                end
+                                                device pci 6.0 on end
+                                        #       end
+                                                device pci 8.0 on end
#intel 10/100
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2885/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2885/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2885/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -121,9 +121,7 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # broadcom 5703
-                                                end
+                                                device pci 9.0 on end #
broadcom 5703
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -137,9 +135,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci b.0
on end # SiI 3114
-                                                end
+                                                device pci b.0 on end #
SiI 3114
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2885/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2885/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2885/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -19,9 +19,7 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # broadcom 5703
-                                                end
+                                                device pci 9.0 on end #
broadcom 5703
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -35,9 +33,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci b.0
on end # SiI 3114
-                                                end
+                                                device pci b.0 on end #
SiI 3114
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2891/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2891/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2891/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -104,9 +104,7 @@
 					device pci 8.0 on end # SATA 0
 					device pci 9.0 on  # PCI
 					#	chip drivers/ati/ragexl
-						chip drivers/pci/onboard
-							device pci 7.0
on end
-						end
+						device pci 7.0 on end
 					end
 					device pci a.0 off end # NIC
 					device pci b.0 off end # PCI E 3
@@ -127,10 +125,8 @@
 					device pci 0.0 on end
 					device pci 0.1 on end
 					device pci 1.0 on
-						chip drivers/pci/onboard
-							device pci 9.0
on end
-							device pci 9.1
on end
-						end
+						device pci 9.0 on end
+						device pci 9.1 on end
 					end
 					device pci 1.1 on end
 				end

Modified: trunk/src/mainboard/tyan/s2892/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2892/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2892/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -105,12 +105,9 @@
 					device pci 8.0 on end # SATA 0
 					device pci 9.0 on  # PCI
 					#	chip drivers/ati/ragexl
-						chip drivers/pci/onboard
-							device pci 6.0
on end
-						end
-						chip drivers/pci/onboard
-							device pci 8.0
on end
-						end
+						device pci 6.0 on end
+					#	end
+						device pci 8.0 on end
 					end
 					device pci a.0 off end # NIC
 					device pci b.0 off end # PCI E 3
@@ -131,10 +128,8 @@
 					device pci 0.0 on end
 					device pci 0.1 on end
 					device pci 1.0 on
-						chip drivers/pci/onboard
-							device pci 9.0
on end # broadcom 5704
-							device pci 9.1
on end
-						end
+						device pci 9.0 on end #
broadcom 5704
+						device pci 9.1 on end
 					end
 					device pci 1.1 on end
 				end

Modified: trunk/src/mainboard/tyan/s2895/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2895/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2895/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -111,10 +111,8 @@
 					device pci 0.0 on end
 					device pci 0.1 on end
 					device pci 1.0 on
-						chip drivers/pci/onboard
-							device pci 6.0
on end # lsi scsi
-							device pci 6.1
on end
-						end
+						device pci 6.0 on end #
lsi scsi
+						device pci 6.1 on end
 					end
 					device pci 1.1 on end
 				end

Modified: trunk/src/mainboard/tyan/s2912_fam10/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2912_fam10/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -279,9 +279,7 @@
 					device pci 5.1 on end # SATA 1
 					device pci 5.2 on end # SATA 2
 					device pci 6.0 on
-						chip drivers/pci/onboard
-							device pci 4.0
on end
-						end
+						device pci 4.0 on end
 					end # PCI
 					device pci 6.1 off end # AZA
 					device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -112,9 +112,7 @@
 					device pci 5.1 on end # SATA 1
 					device pci 5.2 on end # SATA 2
 					device pci 6.0 on
-						chip drivers/pci/onboard
-							device pci 4.0
on end
-						end
+						device pci 4.0 on end
 					end # PCI
 					device pci 6.1 off end # AZA
 					device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/tyan/s4880/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s4880/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s4880/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -116,10 +116,8 @@
 #                                                        device pci 4.1
on end
 #                                                        register
"fw_address" = "0xfff8c000"
 #                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end
-                                                        device pci 9.1
on end
-                                                end
+                                                device pci 9.0 on end
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -133,9 +131,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s4880/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s4880/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -19,10 +19,8 @@
 #                                                        device pci 4.1
on end
 #                                                        register
"fw_address" = "0xfff8c000"
 #                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end
-                                                        device pci 9.1
on end
-                                                end
+                                                device pci 9.0 on end
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -36,9 +34,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s4882/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s4882/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s4882/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -114,10 +114,8 @@
 #							device pci 4.1
on end
 #							register
"fw_address" = "0xfff8c000"
 #						end
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end #Broadcom
-                                                        device pci 9.1
on end
-                                                end 
+                                                device pci 9.0 on end
#Broadcom
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -132,12 +130,9 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip
drivers/ati/ragexl
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end #SiI
-                                                end
+                                                device pci 6.0 on end
+                                                #end
+                                                device pci 5.0 on end
#SiI
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s4882/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s4882/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -17,10 +17,8 @@
 #							device pci 4.1
on end
 #							register
"fw_address" = "0xfff8c000"
 #						end
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end #Broadcom
-                                                        device pci 9.1
on end
-                                                end 
+                                                device pci 9.0 on end
#Broadcom
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -35,12 +33,9 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip
drivers/ati/ragexl
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end #SiI
-                                                end
+                                                device pci 6.0 on end
+                                                #end
+                                                device pci 5.0 on end
#SiI
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/via/epia/Config.lb
===================================================================
--- trunk/src/mainboard/via/epia/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/via/epia/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -96,10 +96,7 @@
 	device pci_domain 0 on
     		device pci 0.0 on end			# Northbridge
 #		device pci 0.1 on			# AGP bridge
-		#	chip drivers/pci/onboard	# Integrated VGA
-		#		device pci 0.0 on end
-		#		register "rom_adress" = "0xfff80000"
-		#	end
+		#	device pci 0.0 on end		# Integrated VGA
 #		end
 		chip southbridge/via/vt8231
 			register "enable_native_ide" = "0"

Modified: trunk/src/mainboard/via/epia/devicetree.cb
===================================================================
--- trunk/src/mainboard/via/epia/devicetree.cb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/via/epia/devicetree.cb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -2,10 +2,7 @@
 	device pci_domain 0 on
     		device pci 0.0 on end			# Northbridge
 #		device pci 0.1 on			# AGP bridge
-		#	chip drivers/pci/onboard	# Integrated VGA
-		#		device pci 0.0 on end
-		#		register "rom_adress" = "0xfff80000"
-		#	end
+		#	device pci 0.0 on end		# Integrated VGA
 #		end
 		chip southbridge/via/vt8231
 			register "enable_native_ide" = "0"

Modified: trunk/src/mainboard/via/vt8454c/Config.lb
===================================================================
--- trunk/src/mainboard/via/vt8454c/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/via/vt8454c/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -121,9 +121,7 @@
 		device pci 0.4 on end # Power Management
 		device pci 0.7 on end # V-Link Controller
 		device pci 1.0 on     # PCI Bridge
-			chip drivers/pci/onboard
-				device pci 0.0 on end
-			end # Onboard Video
+			device pci 0.0 on end # Onboard Video
 		end # PCI Bridge
 		device pci f.0 on end # IDE/SATA
 		#device pci f.1 on end # IDE

Modified: trunk/src/mainboard/via/vt8454c/devicetree.cb
===================================================================
--- trunk/src/mainboard/via/vt8454c/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/via/vt8454c/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -12,9 +12,7 @@
 		device pci 0.4 on end # Power Management
 		device pci 0.7 on end # V-Link Controller
 		device pci 1.0 on     # PCI Bridge
-			chip drivers/pci/onboard
-				device pci 0.0 on end
-			end # Onboard Video
+			device pci 0.0 on end # Onboard Video
 		end # PCI Bridge
 		device pci f.0 on end # IDE/SATA
 		#device pci f.1 on end # IDE

Modified: trunk/src/northbridge/via/cn400/vga.c
===================================================================
--- trunk/src/northbridge/via/cn400/vga.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/northbridge/via/cn400/vga.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -121,15 +121,8 @@
 #endif
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = 0xfff80000;
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static const struct device_operations vga_operations = {
-	.read_resources   = vga_read_resources,
+	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = vga_init,

Modified: trunk/src/northbridge/via/cn700/vga.c
===================================================================
--- trunk/src/northbridge/via/cn700/vga.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/northbridge/via/cn700/vga.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -101,15 +101,8 @@
 	memset(0xf0000, 0, 0x10000);
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = 0xfff80000;
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static const struct device_operations vga_operations = {
-	.read_resources   = vga_read_resources,
+	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = vga_init,

Modified: trunk/src/northbridge/via/cx700/cx700_vga.c
===================================================================
--- trunk/src/northbridge/via/cx700/cx700_vga.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/northbridge/via/cx700/cx700_vga.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -97,15 +97,8 @@
 	outb(reg8, SR_DATA);
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = 0xfff80000;
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static struct device_operations vga_operations = {
-	.read_resources = vga_read_resources,
+	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = vga_init,

Modified: trunk/src/northbridge/via/vt8623/northbridge.c
===================================================================
--- trunk/src/northbridge/via/vt8623/northbridge.c	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/northbridge/via/vt8623/northbridge.c	2009-11-06
23:42:26 UTC (rev 4925)
@@ -124,9 +124,6 @@
 	
 #if 0
 	/* code to make vga init go through the emulator - as of yet
this does not workfor the epia-m */
-	dev->on_mainboard=1;
-	dev->rom_address = (void *)0xfffc0000;
-
 	pci_dev_init(dev);
 	
 	call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
@@ -167,17 +164,8 @@
 #endif
 }
 
-static void vga_read_resources(device_t dev)
-{
-
-	dev->rom_address = (void *)0xfffc0000;
-	dev->on_mainboard=1;
-	pci_dev_read_resources(dev);
-
-}
-
 static struct device_operations vga_operations = {
-	.read_resources   = vga_read_resources,
+	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = vga_init,

Modified: trunk/src/northbridge/via/vx800/vga.c
===================================================================
--- trunk/src/northbridge/via/vx800/vga.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/northbridge/via/vx800/vga.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -126,15 +126,8 @@
 
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = (void *)(0xffffffff - CONFIG_ROM_SIZE + 1);
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static struct device_operations vga_operations = {
-	.read_resources = vga_read_resources,
+	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = vga_init,

Modified: trunk/src/southbridge/nvidia/ck804/chip.h
===================================================================
--- trunk/src/southbridge/nvidia/ck804/chip.h	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/southbridge/nvidia/ck804/chip.h	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -7,8 +7,6 @@
 	unsigned int ide1_enable : 1;
 	unsigned int sata0_enable : 1;
 	unsigned int sata1_enable : 1;
-	unsigned long nic_rom_address;
-	unsigned long raid_rom_address;
 	unsigned int mac_eeprom_smbus;
 	unsigned int mac_eeprom_addr;
 };

Modified: trunk/src/southbridge/nvidia/ck804/ck804.c
===================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/southbridge/nvidia/ck804/ck804.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -77,12 +77,10 @@
 	case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
 		devfn -= (9 << 3);
 		index = 10;
-		dev->rom_address = conf->nic_rom_address;
 		break;
 	case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
 		devfn -= (9 << 3);
 		index = 10;
-		dev->rom_address = conf->nic_rom_address;
 		break;
 	case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
 		devfn -= (3 << 3);
@@ -95,7 +93,6 @@
 	case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
 		devfn -= (5 << 3);
 		index = 14;
-		dev->rom_address = conf->raid_rom_address;
 		break;
 	case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
 		devfn -= (6 << 3);
Myles Watson - 2009-11-09 16:03:07
> R4925 makes my linux hang. Output is attached.
> My board is K8+rs780+sb700, which is close to dbm690t(k8+rs690+sb700).
> But dbm690t works well. I don't know why.
Can you send the log from r4924?

Thanks,
Myles
Bao, Zheng - 2009-11-10 02:08:20
Log from r4924.



-----Original Message-----
From: Myles Watson [mailto:mylesgw@gmail.com] 
Sent: Tuesday, November 10, 2009 12:03 AM
To: Bao, Zheng; coreboot@coreboot.org
Cc: 'Carl-Daniel Hailfinger'; 'Stefan Reinauer'; 'Marc Jones'
Subject: RE: [coreboot] [v2] r4925 makes my linux hang

> R4925 makes my linux hang. Output is attached.
> My board is K8+rs780+sb700, which is close to dbm690t(k8+rs690+sb700).
> But dbm690t works well. I don't know why.
Can you send the log from r4924?

Thanks,
Myles
Myles Watson - 2009-11-10 03:31:13
> Log from r4924.
The problem is that the video card gets treated as if it were part of the
RS780.  In many chipsets, there's a check to see if the device is really
part of the chipset before it is initialized using the chipset functions.


rs780_enable: dev=000231dc, VID_DID=0x96151002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x000202f0, dev=0x000231dc, port=0x00000005
PcieLinkTraining port=5:lc current state=0
PcieTrainPort port=0x5 result=0
PCI: 01:05.0 [1002/9615] ops

Maybe we need some way to say "use the default" still?  chip default_ops or
something?

Thanks,
Myles
Bao, Zheng - 2009-11-10 03:54:44
By "we", please tell me if it has anything to do with the chipset and
mainboard code.

Zheng

-----Original Message-----
From: Myles Watson [mailto:mylesgw@gmail.com] 
Sent: Tuesday, November 10, 2009 11:31 AM
To: Bao, Zheng; coreboot@coreboot.org
Cc: 'Carl-Daniel Hailfinger'; 'Stefan Reinauer'; 'Marc Jones'
Subject: RE: [coreboot] [v2] r4925 makes my linux hang


> Log from r4924.
The problem is that the video card gets treated as if it were part of
the
RS780.  In many chipsets, there's a check to see if the device is really
part of the chipset before it is initialized using the chipset
functions.


rs780_enable: dev=000231dc, VID_DID=0x96151002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x000202f0, dev=0x000231dc, port=0x00000005
PcieLinkTraining port=5:lc current state=0
PcieTrainPort port=0x5 result=0
PCI: 01:05.0 [1002/9615] ops

Maybe we need some way to say "use the default" still?  chip default_ops
or
something?

Thanks,
Myles
Myles Watson - 2009-11-10 04:06:37
On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng <Zheng.Bao@amd.com> wrote:
> By "we", please tell me if it has anything to do with the chipset and
> mainboard code.
Sorry I wasn't clear.  I meant maybe coreboot needs a generic chip driver.

I think the 780 code needs to check the device to make sure it's part
of the chipset before initializing the devices.

Thanks,
Myles
Myles Watson - 2009-11-10 15:45:43
On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson <mylesgw@gmail.com> wrote:

> On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng <Zheng.Bao@amd.com> wrote:
> > By "we", please tell me if it has anything to do with the chipset and
> > mainboard code.
> Sorry I wasn't clear.  I meant maybe coreboot needs a generic chip driver.
>
> I think the 780 code needs to check the device to make sure it's part
> of the chipset before initializing the devices.
>
Could you send me your devicetree.cb or Config.lb?
Thanks,
Myles
Myles Watson - 2009-11-10 15:59:32
On Tue, Nov 10, 2009 at 9:45 AM, Myles Watson <mylesgw@gmail.com> wrote:

>
>
> On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson <mylesgw@gmail.com> wrote:
>
>> On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng <Zheng.Bao@amd.com> wrote:
>> > By "we", please tell me if it has anything to do with the chipset and
>> > mainboard code.
>> Sorry I wasn't clear.  I meant maybe coreboot needs a generic chip driver.
>>
>> I think the 780 code needs to check the device to make sure it's part
>> of the chipset before initializing the devices.
>>
> Could you send me your devicetree.cb or Config.lb?
>
> My thought is that you can put chip drivers/generic/generic around the
video card so that it doesn't get the 780 ops.

Thanks,
Myles
Stefan Reinauer - 2009-11-10 16:05:11
Myles Watson wrote:
>
>
> On Tue, Nov 10, 2009 at 9:45 AM, Myles Watson <mylesgw@gmail.com
> <mailto:mylesgw@gmail.com>> wrote:
>
>
>
>     On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson <mylesgw@gmail.com
>     <mailto:mylesgw@gmail.com>> wrote:
>
>         On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng <Zheng.Bao@amd.com
>         <mailto:Zheng.Bao@amd.com>> wrote:
>         > By "we", please tell me if it has anything to do with the
>         chipset and
>         > mainboard code.
>         Sorry I wasn't clear.  I meant maybe coreboot needs a generic
>         chip driver.
>
>         I think the 780 code needs to check the device to make sure
>         it's part
>         of the chipset before initializing the devices.
>
>     Could you send me your devicetree.cb or Config.lb?
>
> My thought is that you can put chip drivers/generic/generic around the
> video card so that it doesn't get the 780 ops.

Does it get any 780 ops at all? I'd think it only does when a struct
pci_driver is catching it?

Stefan
Myles Watson - 2009-11-10 16:29:56
> >     Could you send me your devicetree.cb or Config.lb?
> >
> > My thought is that you can put chip drivers/generic/generic around the
> > video card so that it doesn't get the 780 ops.
> 
> Does it get any 780 ops at all? I'd think it only does when a struct
> pci_driver is catching it?

I haven't seen the device tree, but the 780 code is initializing it.  That
seems to be the only difference between the failing and functioning logs.

Thanks,
Myles
Bao, Zheng - 2009-11-11 03:03:40
Config.lb and lspci of mahogany and mahogany_fam10 are attached. 

 

Zheng
Peter Stuge - 2009-11-11 03:33:09
Config.lb_mahogany_k8
> chip southbridge/amd/rs780
> 	device pci 0.0 on end # HT  	0x9600
> 	device pci 1.0 on  # Internal Graphics P2P bridge 0x9602
> 		chip drivers/pci/onboard
> 			device pci 5.0 on end	# Internal Graphics 0x9615
> 			register "rom_address" = "0xfff00000"
> 		end
> 	end

I think onboard was removed, and also rom_address because CBFS can be
used to find the ROM.

I'm not sure how to best "decouple" the graphics device from the 780.


//Peter
Bao, Zheng - 2009-11-11 03:38:44
The onboard was not removed because all my work have based on 4924,
which has remove the onboard. If I need try the new code, I will remove
it.


Zheng

-----Original Message-----
From: coreboot-bounces@coreboot.org
[mailto:coreboot-bounces@coreboot.org] On Behalf Of Peter Stuge
Sent: Wednesday, November 11, 2009 11:33 AM
To: coreboot@coreboot.org
Subject: Re: [coreboot] [v2] r4925 makes my linux hang

Config.lb_mahogany_k8
> chip southbridge/amd/rs780
> 	device pci 0.0 on end # HT  	0x9600
> 	device pci 1.0 on  # Internal Graphics P2P bridge 0x9602
> 		chip drivers/pci/onboard
> 			device pci 5.0 on end	# Internal Graphics
0x9615
> 			register "rom_address" = "0xfff00000"
> 		end
> 	end

I think onboard was removed, and also rom_address because CBFS can be
used to find the ROM.

I'm not sure how to best "decouple" the graphics device from the 780.


//Peter
Stefan Reinauer - 2009-11-11 10:34:30
Peter Stuge wrote:
> Config.lb_mahogany_k8
>   
>> chip southbridge/amd/rs780
>> 	device pci 0.0 on end # HT  	0x9600
>> 	device pci 1.0 on  # Internal Graphics P2P bridge 0x9602
>> 		chip drivers/pci/onboard
>> 			device pci 5.0 on end	# Internal Graphics 0x9615
>> 			register "rom_address" = "0xfff00000"
>> 		end
>> 	end
>>     

I would think the above does not compile anymore with HEAD.


> I think onboard was removed, and also rom_address because CBFS can be
> used to find the ROM.
>
> I'm not sure how to best "decouple" the graphics device from the 780.
>   
What do you mean by decouple?

There is likely a

static struct pci_driver pcie_driver_780 __pci_driver = {
        .ops = &pcie_ops,
        .vendor = PCI_VENDOR_ID_ATI,
        .device = PCI_DEVICE_ID_ATI_RS780_INT_GFX,
};

and that is why a non-standard .ops is associated with that device.

If the problem is chip_ops:

This is how it should look if the graphics device is supposed to have
the chip_ops of the 780 attached (ie the internal graphicsw can use
values from struct southbridge_amd_rs780_config

chip southbridge/amd/rs780
	device pci 0.0 on end # HT  	0x9600
	device pci 1.0 on  # Internal Graphics P2P bridge 0x9602
		device pci 5.0 on end	# Internal Graphics 0x9615
	end

This is different from the old behavior, however... It gives a different
set of chip_ops to the internal graphics chip:

struct chip_operations southbridge_amd_rs780_ops = {
        CHIP_NAME("AMD RS780 Northbridge")
        .enable_dev = enable_dev,
};

Now, I don't know the RS780 code but if it is based on/similar to the
RS690 code I think I know what's wrong.


This is from RS690:
/***********************************************
*       0:00.0  NBCFG   :
*       0:00.1  CLK     : bit 0 of nb_cfg 0x4c : 0 - disable, default
*       0:01.0  P2P Internal:
*       0:02.0  P2P     : bit 2 of nbmiscind 0x0c : 0 - enable,
default    + 32 * 2
*       0:03.0  P2P     : bit 3 of nbmiscind 0x0c : 0 - enable,
default    + 32 * 2
*       0:04.0  P2P     : bit 4 of nbmiscind 0x0c : 0 - enable,
default    + 32 * 2
*       0:05.0  P2P     : bit 5 of nbmiscind 0x0c : 0 - enable,
default    + 32 * 2
*       0:06.0  P2P     : bit 6 of nbmiscind 0x0c : 0 - enable,
default    + 32 * 2
*       0:07.0  P2P     : bit 7 of nbmiscind 0x0c : 0 - enable,
default    + 32 * 2
*       0:08.0  NB2SB   : bit 6 of nbmiscind 0x00 : 0 - disable,
default   + 32 * 1
* case 0 will be called twice, one is by cpu in hypertransport.c line458,
* the other is by rs690.
***********************************************/
void rs690_enable(device_t dev)
{
...
        dev_ind = dev->path.pci.devfn >> 3;
        switch (dev_ind) {
        case 0:         /* bus0, dev0, fun0; */
...
        case 1:         /* bus0, dev1 */
                printk_info("Bus-0, Dev-1, Fun-0.\n");
                break;
...
        case 4:         /* bus0, dev4-7, four GPP */
        case 5:
        case 6:
        case 7:
                printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
                            dev->enabled);
                set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
                                       (dev->enabled ? 0 : 1) << dev_ind);
                if (dev->enabled)
                        rs690_gpp_sb_init(nb_dev, dev, dev_ind);
                break;
...
}


Now let's think about that for a minute:

* case 0 will not only match for bus 0, device 0, function 0. Instead it
will ignore bus and function.
   So it will listen to all device 0 that have an ams_rs690_ops called
* The same appears for case 5. Instead of calling it for 0:5.0 it also
gets called for 1:5.0 (or whatever bus gfx is on) and will treat it as a
device that it is not.


The good news is:
chip southbridge/amd/rs780 unconditionally pulls in the graphics driver
which is still executed per PCI ID, and not per notation of static.c

So it's completely enough to drop the graphics device from
Config.lb/devicetree.cb and say

chip southbridge/amd/rs780
	device pci 0.0 on end # HT  	0x9600
	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602


Stefan
Myles Watson - 2009-11-11 14:00:16
> The good news is:
> chip southbridge/amd/rs780 unconditionally pulls in the graphics driver
> which is still executed per PCI ID, and not per notation of static.c
> 
> So it's completely enough to drop the graphics device from
> Config.lb/devicetree.cb and say
> 
> chip southbridge/amd/rs780
> 	device pci 0.0 on end # HT  	0x9600
> 	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
> 
The only downside is that the subsystem IDs won't be set, because the device
will not be "on mainboard" anymore.

Thanks,
Myles
Stefan Reinauer - 2009-11-11 21:26:45
Myles Watson wrote:
>> The good news is:
>> chip southbridge/amd/rs780 unconditionally pulls in the graphics driver
>> which is still executed per PCI ID, and not per notation of static.c
>>
>> So it's completely enough to drop the graphics device from
>> Config.lb/devicetree.cb and say
>>
>> chip southbridge/amd/rs780
>> 	device pci 0.0 on end # HT  	0x9600
>> 	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
>>
>>     
> The only downside is that the subsystem IDs won't be set, because the device
> will not be "on mainboard" anymore.
>   
It should be set, since there is a driver for that device....
Myles Watson - 2009-11-11 21:29:49
On Wed, Nov 11, 2009 at 2:26 PM, Stefan Reinauer <stepan@coresystems.de> wrote:
> Myles Watson wrote:
>>> The good news is:
>>> chip southbridge/amd/rs780 unconditionally pulls in the graphics driver
>>> which is still executed per PCI ID, and not per notation of static.c
>>>
>>> So it's completely enough to drop the graphics device from
>>> Config.lb/devicetree.cb and say
>>>
>>> chip southbridge/amd/rs780
>>>      device pci 0.0 on end # HT      0x9600
>>>      device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
>>>
>>>
>> The only downside is that the subsystem IDs won't be set, because the device
>> will not be "on mainboard" anymore.
>>
> It should be set, since there is a driver for that device....
Great.  I thought it only got set if it was found in the device tree.

Thanks,
Myles
Stefan Reinauer - 2009-11-11 21:30:08
Myles Watson wrote:
>> The good news is:
>> chip southbridge/amd/rs780 unconditionally pulls in the graphics driver
>> which is still executed per PCI ID, and not per notation of static.c
>>
>> So it's completely enough to drop the graphics device from
>> Config.lb/devicetree.cb and say
>>
>> chip southbridge/amd/rs780
>> 	device pci 0.0 on end # HT  	0x9600
>> 	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
>>
>>     
> The only downside is that the subsystem IDs won't be set, because the device
> will not be "on mainboard" anymore.

... a viable alternative is fixing the chip's enable_dev to take the bus
and function number into regard.

Stefan
Bao, Zheng - 2009-11-13 04:06:54
Great!!

It fixes the hanging on my board. And the display also works. Everything
seems to be fine.


Zheng

-----Original Message-----
From: coreboot-bounces@coreboot.org
[mailto:coreboot-bounces@coreboot.org] On Behalf Of Stefan Reinauer
Sent: Thursday, November 12, 2009 5:30 AM
To: Myles Watson
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] [v2] r4925 makes my linux hang

Myles Watson wrote:
>> The good news is:
>> chip southbridge/amd/rs780 unconditionally pulls in the graphics
driver
>> which is still executed per PCI ID, and not per notation of static.c
>>
>> So it's completely enough to drop the graphics device from
>> Config.lb/devicetree.cb and say
>>
>> chip southbridge/amd/rs780
>> 	device pci 0.0 on end # HT  	0x9600
>> 	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
>>
>>     
> The only downside is that the subsystem IDs won't be set, because the
device
> will not be "on mainboard" anymore.

... a viable alternative is fixing the chip's enable_dev to take the bus
and function number into regard.

Stefan
Bao, Zheng - 2009-11-13 05:31:22
Other boards like 690/600 need to modify, don't they?

Zheng

-----Original Message-----
From: coreboot-bounces@coreboot.org
[mailto:coreboot-bounces@coreboot.org] On Behalf Of Bao, Zheng
Sent: Friday, November 13, 2009 12:07 PM
To: Stefan Reinauer; Myles Watson
Cc: Marc Jones; coreboot@coreboot.org
Subject: Re: [coreboot] [v2] r4925 makes my linux hang

Great!!

It fixes the hanging on my board. And the display also works. Everything
seems to be fine.


Zheng

-----Original Message-----
From: coreboot-bounces@coreboot.org
[mailto:coreboot-bounces@coreboot.org] On Behalf Of Stefan Reinauer
Sent: Thursday, November 12, 2009 5:30 AM
To: Myles Watson
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] [v2] r4925 makes my linux hang

Myles Watson wrote:
>> The good news is:
>> chip southbridge/amd/rs780 unconditionally pulls in the graphics
driver
>> which is still executed per PCI ID, and not per notation of static.c
>>
>> So it's completely enough to drop the graphics device from
>> Config.lb/devicetree.cb and say
>>
>> chip southbridge/amd/rs780
>> 	device pci 0.0 on end # HT  	0x9600
>> 	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
>>
>>     
> The only downside is that the subsystem IDs won't be set, because the
device
> will not be "on mainboard" anymore.

... a viable alternative is fixing the chip's enable_dev to take the bus
and function number into regard.

Stefan
Myles Watson - 2009-11-13 16:33:47
> Other boards like 690/600 need to modify, don't they?
I don't have any boards with those chipsets.  I thought you said the dbm690t
was fine, but I don't know for sure.

Thanks,
Myles
Bao, Zheng - 2009-11-16 06:30:01
Now my VGA BIOS seems to run incorrectly.

Without_entry.txt:
The output of image running with Config.lb like,
chip southbridge/amd/rs780
 	device pci 0.0 on end # HT  	0x9600
 	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602

With_entry.txt:
The output of image running with Config.lib like
 chip southbridge/amd/rs780
	device pci 0.0 on  # HT  	0x9600
               device pci 5.0 on end
	end
 	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602

That only happens when the CPU is K8. When the cpu is fam10, VGA runs
ok.
Any advice?



Zheng


-----Original Message-----
From: Myles Watson [mailto:mylesgw@gmail.com] 
Sent: Saturday, November 14, 2009 12:34 AM
To: Bao, Zheng; 'Stefan Reinauer'
Cc: 'Marc Jones'; coreboot@coreboot.org
Subject: RE: [coreboot] [v2] r4925 makes my linux hang

> Other boards like 690/600 need to modify, don't they?
I don't have any boards with those chipsets.  I thought you said the
dbm690t
was fine, but I don't know for sure.

Thanks,
Myles
CPU model AMD Athlon(tm) 64 Processor 3000+
Setting up local apic... apic_id: 0x00 done.
ECC Disabled
CPU #0 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:00.0 init
pcie_init in rs780_ht.c
PCI: 00:11.0 init
sata_bar0=3020
sata_bar1=3040
sata_bar2=3028
sata_bar3=3044
sata_bar4=3000
sata_bar5=d0209000
SATA port 0 status = 0
No Primary Master SATA drive on Slot0
SATA port 1 status = 0
No Primary Slave SATA drive on Slot1
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3
PCI: 00:12.0 init
PCI: 00:12.1 init
PCI: 00:12.2 init
usb2_bar0=d0209400
PCI: 00:13.0 init
PCI: 00:13.1 init
PCI: 00:13.2 init
usb2_bar0=d0209500
PCI: 00:14.0 init
sm_init().
lapicid = 0000000000000000
set power on after power fail
++++++++++no set NMI+++++
RTC Init
sm_init() end
PCI: 00:14.1 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11c6c + align -> fff27780
Check fallback/payload
CBFS: follow chain: fff27780 + 38 + 15a68 + align -> fff3d240
Check fallback/coreboot_ram
CBFS: follow chain: fff3d240 + 38 + 11c70 + align -> fff4ef00
Check pci1002,9615.rom
CBFS: follow chain: fff4ef00 + 38 + ec00 + align -> fff5db40
Check
CBFS: follow chain: fff5db40 + 28 + 72478 + align -> fffd0000
CBFS:  Could not find file pci1002,439c.rom
PCI: 00:14.2 init
base = d0200000
codec_mask = 01
codec viddid: 10ec0888
Dev=PCI: 00:14.2
Default viddid=10ec0882
Reading viddid=10ec0888
No verb!
PCI: 00:14.3 init
PNP: 002e.1 init
PNP: 002e.5 init
Keyboard init...
Keyboard selftest failed ACK: 0xfe
PCI: 00:14.4 init
PCI: 00:14.5 init
PCI: 00:18.1 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11c6c + align -> fff27780
Check fallback/payload
CBFS: follow chain: fff27780 + 38 + 15a68 + align -> fff3d240
Check fallback/coreboot_ram
CBFS: follow chain: fff3d240 + 38 + 11c70 + align -> fff4ef00
Check pci1002,9615.rom
CBFS: follow chain: fff4ef00 + 38 + ec00 + align -> fff5db40
Check
CBFS: follow chain: fff5db40 + 28 + 72478 + align -> fffd0000
CBFS:  Could not find file pci1022,1101.rom
PCI: 00:18.2 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11c6c + align -> fff27780
Check fallback/payload
CBFS: follow chain: fff27780 + 38 + 15a68 + align -> fff3d240
Check fallback/coreboot_ram
CBFS: follow chain: fff3d240 + 38 + 11c70 + align -> fff4ef00
Check pci1002,9615.rom
CBFS: follow chain: fff4ef00 + 38 + ec00 + align -> fff5db40
Check
CBFS: follow chain: fff5db40 + 28 + 72478 + align -> fffd0000
CBFS:  Could not find file pci1022,1102.rom
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 01:05.0 init
internal_gfx_pci_dev_init device=9615, vendor=1002.
MEMCLK = 3
NB HT speed = 1c750660.
CPU HT speed = 80750622.
HT width = 11110020.
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11c6c + align -> fff27780
Check fallback/payload
CBFS: follow chain: fff27780 + 38 + 15a68 + align -> fff3d240
Check fallback/coreboot_ram
CBFS: follow chain: fff3d240 + 38 + 11c70 + align -> fff4ef00
Check pci1002,9615.rom
In cbfs, rom address for PCI: 01:05.0 = fff4ef38
PCI Expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x01c0
PCI ROM Image, Vendor 1002, Device 9615,
PCI ROM Image,  Class Code 030000, Code Type 00
copying VGA ROM Image from fff4ef38 to 0xc0000, 0xec00 bytes
Executing Initialization Vector...
MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU model AMD Athlon(tm) 64 Processor 3000+
Setting up local apic... apic_id: 0x00 done.
ECC Disabled
CPU #0 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:00.0 init
pcie_init in rs780_ht.c
PCI: 01:05.0 init
internal_gfx_pci_dev_init device=9615, vendor=1002.
MEMCLK = 3
NB HT speed = 1c750660.
CPU HT speed = 80750622.
HT width = 11110020.
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11cb2 + align -> fff277c0
Check fallback/payload
CBFS: follow chain: fff277c0 + 38 + 15a68 + align -> fff3d280
Check fallback/coreboot_ram
CBFS: follow chain: fff3d280 + 38 + 11cd2 + align -> fff4efc0
Check pci1002,9615.rom
In cbfs, rom address for PCI: 01:05.0 = fff4eff8
PCI Expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x01c0
PCI ROM Image, Vendor 1002, Device 9615,
PCI ROM Image,  Class Code 030000, Code Type 00
copying VGA ROM Image from fff4eff8 to 0xc0000, 0xec00 bytes
Executing Initialization Vector...
Option ROM Exit Status: ffb6
Stack unclean, initialization probably NOT COMPLETE!!
SS:SP = 1000:ff66, expected: 1000:fffe
PCI: 00:11.0 init
sata_bar0=3020
sata_bar1=3040
sata_bar2=3028
sata_bar3=3044
sata_bar4=3000
sata_bar5=d0209000
SATA port 0 status = 0
No Primary Master SATA drive on Slot0
SATA port 1 status = 0
No Primary Slave SATA drive on Slot1
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3
PCI: 00:12.0 init
PCI: 00:12.1 init
PCI: 00:12.2 init
usb2_bar0=d0209400
PCI: 00:13.0 init
PCI: 00:13.1 init
PCI: 00:13.2 init
usb2_bar0=d0209500
PCI: 00:14.0 init
sm_init().
lapicid = 0000000000000000
set power on after power fail
++++++++++no set NMI+++++
RTC Init
sm_init() end
PCI: 00:14.1 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11cb2 + align -> fff277c0
Check fallback/payload
CBFS: follow chain: fff277c0 + 38 + 15a68 + align -> fff3d280
Check fallback/coreboot_ram
CBFS: follow chain: fff3d280 + 38 + 11cd2 + align -> fff4efc0
Check pci1002,9615.rom
CBFS: follow chain: fff4efc0 + 38 + ec00 + align -> fff5dc00
Check
CBFS: follow chain: fff5dc00 + 28 + 723b8 + align -> fffd0000
CBFS:  Could not find file pci1002,439c.rom
PCI: 00:14.2 init
base = d0200000
codec_mask = 01
codec viddid: 10ec0888
Dev=PCI: 00:14.2
Default viddid=10ec0882
Reading viddid=10ec0888
No verb!
PCI: 00:14.3 init
PNP: 002e.1 init
PNP: 002e.5 init
Keyboard init...
Keyboard selftest failed ACK: 0xfe
PCI: 00:14.4 init
PCI: 00:14.5 init
PCI: 00:18.1 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11cb2 + align -> fff277c0
Check fallback/payload
CBFS: follow chain: fff277c0 + 38 + 15a68 + align -> fff3d280
Check fallback/coreboot_ram
CBFS: follow chain: fff3d280 + 38 + 11cd2 + align -> fff4efc0
Check pci1002,9615.rom
CBFS: follow chain: fff4efc0 + 38 + ec00 + align -> fff5dc00
Check
CBFS: follow chain: fff5dc00 + 28 + 723b8 + align -> fffd0000
CBFS:  Could not find file pci1022,1101.rom
PCI: 00:18.2 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11cb2 + align -> fff277c0
Check fallback/payload
CBFS: follow chain: fff277c0 + 38 + 15a68 + align -> fff3d280
Check fallback/coreboot_ram
CBFS: follow chain: fff3d280 + 38 + 11cd2 + align -> fff4efc0
Check pci1002,9615.rom
CBFS: follow chain: fff4efc0 + 38 + ec00 + align -> fff5dc00
Check
CBFS: follow chain: fff5dc00 + 28 + 723b8 + align -> fffd0000
CBFS:  Could not find file pci1022,1102.rom
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 03:00.0 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11cb2 + align -> fff277c0
Check fallback/payload
CBFS: follow chain: fff277c0 + 38 + 15a68 + align -> fff3d280
Check fallback/coreboot_ram
CBFS: follow chain: fff3d280 + 38 + 11cd2 + align -> fff4efc0
Check pci1002,9615.rom
CBFS: follow chain: fff4efc0 + 38 + ec00 + align -> fff5dc00
Check
CBFS: follow chain: fff5dc00 + 28 + 723b8 + align -> fffd0000
CBFS:  Could not find file pci10ec,8168.rom
On card, rom address for PCI: 03:00.0 = d0100000
PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect Expansion ROM Header Signature 0000
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 4 resources
PCI: 00:18.0: enabled 1, 4 resources
PCI: 00:00.0: enabled 1, 1 resources
PCI: 00:01.0: enabled 1, 3 resources
PCI: 01:05.0: enabled 1, 3 resources
PCI: 00:02.0: enabled 0, 0 resources
PCI: 00:03.0: enabled 0, 0 resources
PCI: 00:04.0: enabled 1, 3 resources
PCI: 00:05.0: enabled 0, 0 resources
PCI: 00:06.0: enabled 0, 0 resources
PCI: 00:07.0: enabled 0, 0 resources
PCI: 00:08.0: enabled 0, 0 resources
PCI: 00:09.0: enabled 1, 3 resources
PCI: 00:0a.0: enabled 1, 3 resources
PCI: 00:11.0: enabled 1, 6 resources
PCI: 00:12.0: enabled 1, 1 resources
PCI: 00:12.1: enabled 1, 1 resources
PCI: 00:12.2: enabled 1, 1 resources
PCI: 00:13.0: enabled 1, 1 resources
PCI: 00:13.1: enabled 1, 1 resources
PCI: 00:13.2: enabled 1, 1 resources
PCI: 00:14.0: enabled 1, 2 resources
I2C: 01:50: enabled 1, 0 resources
I2C: 01:51: enabled 1, 0 resources
I2C: 01:52: enabled 1, 0 resources
I2C: 01:53: enabled 1, 0 resources
PCI: 00:14.1: enabled 1, 5 resources
PCI: 00:14.2: enabled 1, 1 resources
PCI: 00:14.3: enabled 1, 4 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 1, 2 resources
PNP: 002e.2: enabled 0, 4 resources
PNP: 002e.3: enabled 0, 2 resources
PNP: 002e.4: enabled 0, 0 resources
PNP: 002e.5: enabled 1, 3 resources
PNP: 002e.6: enabled 1, 1 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 0, 2 resources
PNP: 002e.9: enabled 0, 1 resources
PNP: 002e.a: enabled 0, 0 resources
PCI: 00:14.4: enabled 1, 3 resources
PCI: 00:14.5: enabled 1, 1 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 1 resources
PCI: 03:00.0: enabled 1, 4 resources
Initializing CBMEM area to 0x6fff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 6fff0200...ok
High Tables Base is 6fff0000.
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0x6fff0400...write_pirq_routing_table done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f0510
Adding CBMEM entry as no. 3
Wrote the mp table end at: 6fff1410 - 6fff1510
MP table: 272 bytes.
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at 6fff2400...
ACPI:    * HPET
ACPI: added table 1/32 Length now 40
ACPI:    * MADT
ACPI: added table 2/32 Length now 44
ACPI:    * SSDT
Unexpected Exception: 6 @ 10:0001ffbb - Halting
Code: 0 eflags: 00010002
eax: 00000806 ebx: 0002744f ecx: 6fff2579 edx: 0000ff01
edi: 6fff2554 esi: 000000ff ebp: 6fff2400 esp: 0003ddd8
Stefan Reinauer - 2009-11-16 07:21:51
Bao, Zheng wrote:
> Now my VGA BIOS seems to run incorrectly.
>
> Without_entry.txt:
> The output of image running with Config.lb like,
> chip southbridge/amd/rs780
>  	device pci 0.0 on end # HT  	0x9600
>  	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
>
> With_entry.txt:
> The output of image running with Config.lib like
>  chip southbridge/amd/rs780
> 	device pci 0.0 on  # HT  	0x9600
>                device pci 5.0 on end
> 	end
>  	device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
>
> That only happens when the CPU is K8. When the cpu is fam10, VGA runs
> ok.
> Any advice?
>   

In the second case it seems to die in ACPI table creation, during VGA
init...

You can try to enable and use the GDB backend to find out where exactly
it dies...

http://www.coreboot.org/Debugging

Stefan
Myles Watson - 2009-11-16 14:20:42
> That only happens when the CPU is K8. When the cpu is fam10, VGA runs
> ok.
> Any advice?

I'd be interested in the complete logs, and a log from a successful fam10 boot.

Thanks,
Myles
Bao, Zheng - 2009-11-17 09:12:24
Here comes the complete logs.

Zheng

-----Original Message-----
From: Myles Watson [mailto:mylesgw@gmail.com] 
Sent: Monday, November 16, 2009 10:21 PM
To: Bao, Zheng
Cc: Stefan Reinauer; Marc Jones; coreboot@coreboot.org
Subject: Re: [coreboot] [v2] r4925 makes my linux hang

> That only happens when the CPU is K8. When the cpu is fam10, VGA runs
> ok.
> Any advice?

I'd be interested in the complete logs, and a log from a successful
fam10 boot.

Thanks,
Myles
Myles Watson - 2009-11-23 15:24:05
> Here comes the complete logs.
I only got the fam10 log, I didn't see the complete k8 logs.

Thanks,
Myles
Bao, Zheng - 2009-11-24 03:19:41
Here comes the complete log. The family 10 is also attached for your
convenience.

Zheng

-----Original Message-----
From: Myles Watson [mailto:mylesgw@gmail.com] 
Sent: Monday, November 23, 2009 11:24 PM
To: Bao, Zheng
Cc: coreboot@coreboot.org
Subject: RE: [coreboot] [v2] r4925 makes my linux hang

> Here comes the complete logs.
I only got the fam10 log, I didn't see the complete k8 logs.

Thanks,
Myles
coreboot-2.0.0-r4952M Tue Nov 24 12:39:23 CST 2009 starting...
bsp_apicid=0x0
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started:
 01SBLink=00
NC node|link=00
rs780_early_setup()
get_cpu_rev EAX=0x60fb2.
CPU Rev is K8_G0.
k8_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
begin msr fid, vid: hi=0x31101616, lo=0x100e0202
Current fid_cur: 0x2, fid_max: 0xe
Requested fid_new: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
set fid failed for apicid =00
end msr fid, vid: hi=0x31101610, lo=0x100e0202
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0xd2, unfiltered freq_cap=0x1c75
pos=0xd2, filtered freq_cap=0x1c75
freq_cap1=0x75, freq_cap2=0x1c75
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
rs780_htinit cpu_ht_freq=6.
rs780_htinit: HT1 mode
needs_reset=0x1
ht reset -


coreboot-2.0.0-r4952M Tue Nov 24 12:39:23 CST 2009 starting...
bsp_apicid=0x0
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started:
 01SBLink=00
NC node|link=00
rs780_early_setup()
get_cpu_rev EAX=0x60fb2.
CPU Rev is K8_G0.
k8_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
begin msr fid, vid: hi=0x31101610, lo=0x100e0202
Current fid_cur: 0x2, fid_max: 0xe
Requested fid_new: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0xe
set fid failed for apicid =00
end msr fid, vid: hi=0x31101610, lo=0x100e0202
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0xd2, unfiltered freq_cap=0x1c75
pos=0xd2, filtered freq_cap=0x1c75
freq_cap1=0x75, freq_cap2=0x1c75
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
rs780_htinit cpu_ht_freq=6.
rs780_htinit: HT1 mode
needs_reset=0x0
sysinfo->nodes:  1  sysinfo->ctrl: cf188  spd_addr: ffff9068
Ram1.00
setting up CPU 00 northbridge registers
done.
Ram2.00
sdram_set_spd_registers: paramx :000ced44
Unbuffered
400MHz
400MHz
RAM end at 0x00100000 kB
Ram3
sdram_enable: tsc0[8]: 000cee04Initializing memory:  done
Setting variable MTRR 2, base:    0MB, range: 1024MB, type WB
DQS Training:RcvrEn:Pass1: 00
 CTLRMaxDelay=03
 done
DQS Training:DQSPos: 00
TrainDQSRdWrPos: buf_a:000ce8d0
TrainDQSPos: MutualCSPassW[48] :000ce7b4
TrainDQSPos: MutualCSPassW[48] :000ce7b4
TrainDQSPos: MutualCSPassW[48] :000ce7b4
TrainDQSPos: MutualCSPassW[48] :000ce7b4
 done
DQS Training:RcvrEn:Pass2: 00
 CTLRMaxDelay=57
 done
DQS SAVE NVRAM: c2000
DQS Training:tsc[00]=0000000025530411
DQS Training:tsc[01]=0000000025fc96bf
DQS Training:tsc[02]=0000000026044ae8
DQS Training:tsc[03]=000000002ae849b4
DQS Training:tsc[04]=000000002b9f415c
Ram4
v_esp=000ceed8
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading stage image.
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11c78 + align -> fff27780
Check fallback/payload
CBFS: follow chain: fff27780 + 38 + 15a68 + align -> fff3d240
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x4000 (245760 bytes), entry @ 0x4000
Stage: done loading.
Jumping to image.
coreboot-2.0.0-r4952M Tue Nov 24 12:39:23 CST 2009 booting...
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:18.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:02.0: enabled 0, 0 resources
PCI: 00:03.0: enabled 0, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PCI: 00:05.0: enabled 0, 0 resources
PCI: 00:06.0: enabled 0, 0 resources
PCI: 00:07.0: enabled 0, 0 resources
PCI: 00:08.0: enabled 0, 0 resources
PCI: 00:09.0: enabled 1, 0 resources
PCI: 00:0a.0: enabled 1, 0 resources
PCI: 00:11.0: enabled 1, 0 resources
PCI: 00:12.0: enabled 1, 0 resources
PCI: 00:12.1: enabled 1, 0 resources
PCI: 00:12.2: enabled 1, 0 resources
PCI: 00:13.0: enabled 1, 0 resources
PCI: 00:13.1: enabled 1, 0 resources
PCI: 00:13.2: enabled 1, 0 resources
PCI: 00:14.0: enabled 1, 0 resources
I2C: 00:50: enabled 1, 0 resources
I2C: 00:51: enabled 1, 0 resources
I2C: 00:52: enabled 1, 0 resources
I2C: 00:53: enabled 1, 0 resources
PCI: 00:14.1: enabled 1, 0 resources
PCI: 00:14.2: enabled 1, 0 resources
PCI: 00:14.3: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 1, 2 resources
PNP: 002e.2: enabled 0, 2 resources
PNP: 002e.3: enabled 0, 2 resources
PNP: 002e.4: enabled 0, 0 resources
PNP: 002e.5: enabled 1, 3 resources
PNP: 002e.6: enabled 1, 1 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 0, 2 resources
PNP: 002e.9: enabled 0, 1 resources
PNP: 002e.a: enabled 0, 0 resources
PCI: 00:14.4: enabled 1, 0 resources
PCI: 00:14.5: enabled 1, 0 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:18.0: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
   PCI: 00:02.0: enabled 0, 0 resources
   PCI: 00:03.0: enabled 0, 0 resources
   PCI: 00:04.0: enabled 1, 0 resources
   PCI: 00:05.0: enabled 0, 0 resources
   PCI: 00:06.0: enabled 0, 0 resources
   PCI: 00:07.0: enabled 0, 0 resources
   PCI: 00:08.0: enabled 0, 0 resources
   PCI: 00:09.0: enabled 1, 0 resources
   PCI: 00:0a.0: enabled 1, 0 resources
   PCI: 00:11.0: enabled 1, 0 resources
   PCI: 00:12.0: enabled 1, 0 resources
   PCI: 00:12.1: enabled 1, 0 resources
   PCI: 00:12.2: enabled 1, 0 resources
   PCI: 00:13.0: enabled 1, 0 resources
   PCI: 00:13.1: enabled 1, 0 resources
   PCI: 00:13.2: enabled 1, 0 resources
   PCI: 00:14.0: enabled 1, 0 resources
    I2C: 00:50: enabled 1, 0 resources
    I2C: 00:51: enabled 1, 0 resources
    I2C: 00:52: enabled 1, 0 resources
    I2C: 00:53: enabled 1, 0 resources
   PCI: 00:14.1: enabled 1, 0 resources
   PCI: 00:14.2: enabled 1, 0 resources
   PCI: 00:14.3: enabled 1, 0 resources
    PNP: 002e.0: enabled 0, 3 resources
    PNP: 002e.1: enabled 1, 2 resources
    PNP: 002e.2: enabled 0, 2 resources
    PNP: 002e.3: enabled 0, 2 resources
    PNP: 002e.4: enabled 0, 0 resources
    PNP: 002e.5: enabled 1, 3 resources
    PNP: 002e.6: enabled 1, 1 resources
    PNP: 002e.7: enabled 0, 0 resources
    PNP: 002e.8: enabled 0, 2 resources
    PNP: 002e.9: enabled 0, 1 resources
    PNP: 002e.a: enabled 0, 0 resources
   PCI: 00:14.4: enabled 1, 0 resources
   PCI: 00:14.5: enabled 1, 0 resources
  PCI: 00:18.1: enabled 1, 0 resources
  PCI: 00:18.2: enabled 1, 0 resources
  PCI: 00:18.3: enabled 1, 0 resources
Mainboard MAHOGANY Enable. dev=0x00028f84
mahogany_enable, TOP MEM: msr.lo = 0x40000000, msr.hi = 0x00000000
mahogany_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
mahogany_enable: uma size 0x10000000, memory start 0x30000000
PCI: Using configuration type 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  PCI: 00:18.3 siblings=1
CPU: APIC: 00 enabled
malloc Enter, size 1092, free_mem_ptr 0003c000
malloc 0003c000
CPU: APIC: 01 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] bus ops
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:18.4, bad id 0xffffffff
PCI: 00:18.5, bad id 0xffffffff
PCI: 00:18.6, bad id 0xffffffff
PCI: 00:18.7, bad id 0xffffffff
PCI: 00:19.0, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0, bad id 0xffffffff
PCI: 00:1e.0, bad id 0xffffffff
PCI: 00:1f.0, bad id 0xffffffff
rs780_enable: dev=0002b1b8, VID_DID=0x96001022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
addr=e0000000,bus=0,devfn=40
gpp_sb_init nb_dev=0x0002b1b8, dev=0x0002d3d8, port=0x00000008
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9600] ops
PCI: 00:00.0 [1022/9600] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0180
PCI: 00:00.0 count: 000c static_count: 0015
PCI: 00:00.0 [1022/9600] enabled next_unitid: 0015
PCI: pci_scan_bus for bus 00
rs780_enable: dev=0002b1b8, VID_DID=0x96001022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0002b1b8, dev=0x0002d3d8, port=0x00000008
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9600] enabled
rs780_enable: dev=0002b5fc, VID_DID=0x96021022
Bus-0, Dev-1, Fun-0.
GC is accessible from now on.
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
PCI: 00:01.0 [1022/9602] enabled
rs780_enable: dev=0002ba40, VID_DID=0x96031022
Bus-0, Dev-2,3, Fun-0. enable=0
PCI: 00:02.1, bad id 0xffffffff
PCI: 00:02.2, bad id 0xffffffff
PCI: 00:02.3, bad id 0xffffffff
PCI: 00:02.4, bad id 0xffffffff
PCI: 00:02.5, bad id 0xffffffff
PCI: 00:02.6, bad id 0xffffffff
PCI: 00:02.7, bad id 0xffffffff
rs780_enable: dev=0002be84, VID_DID=0x960b1022
Bus-0, Dev-2,3, Fun-0. enable=0
PCI: 00:03.1, bad id 0xffffffff
PCI: 00:03.2, bad id 0xffffffff
PCI: 00:03.3, bad id 0xffffffff
PCI: 00:03.4, bad id 0xffffffff
PCI: 00:03.5, bad id 0xffffffff
PCI: 00:03.6, bad id 0xffffffff
PCI: 00:03.7, bad id 0xffffffff
rs780_enable: dev=0002c2c8, VID_DID=0x96041022
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x0002b1b8, dev=0x0002c2c8, port=0x00000004
PcieLinkTraining port=4:lc current state=10203
PcieTrainPort port=0x4 result=0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1022/9604] enabled
rs780_enable: dev=0002c70c, VID_DID=0x96051022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
PCI: 00:05.1, bad id 0xffffffff
PCI: 00:05.2, bad id 0xffffffff
PCI: 00:05.3, bad id 0xffffffff
PCI: 00:05.4, bad id 0xffffffff
PCI: 00:05.5, bad id 0xffffffff
PCI: 00:05.6, bad id 0xffffffff
PCI: 00:05.7, bad id 0xffffffff
rs780_enable: dev=0002cb50, VID_DID=0x96061022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
PCI: 00:06.1, bad id 0xffffffff
PCI: 00:06.2, bad id 0xffffffff
PCI: 00:06.3, bad id 0xffffffff
PCI: 00:06.4, bad id 0xffffffff
PCI: 00:06.5, bad id 0xffffffff
PCI: 00:06.6, bad id 0xffffffff
PCI: 00:06.7, bad id 0xffffffff
rs780_enable: dev=0002cf94, VID_DID=0x96071022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
PCI: 00:07.1, bad id 0xffffffff
PCI: 00:07.2, bad id 0xffffffff
PCI: 00:07.3, bad id 0xffffffff
PCI: 00:07.4, bad id 0xffffffff
PCI: 00:07.5, bad id 0xffffffff
PCI: 00:07.6, bad id 0xffffffff
PCI: 00:07.7, bad id 0xffffffff
rs780_enable: dev=0002d3d8, VID_DID=0xffffffff
Bus-0, Dev-8, Fun-0. enable=0
disable_pcie_bar3()
PCI: 00:08.1, bad id 0xffffffff
PCI: 00:08.2, bad id 0xffffffff
PCI: 00:08.3, bad id 0xffffffff
PCI: 00:08.4, bad id 0xffffffff
PCI: 00:08.5, bad id 0xffffffff
PCI: 00:08.6, bad id 0xffffffff
PCI: 00:08.7, bad id 0xffffffff
rs780_enable: dev=0002d81c, VID_DID=0x96081022
Bus-0, Dev-9, 10, Fun-0. enable=1
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0002b1b8, dev=0x0002d81c, port=0x00000009
PcieLinkTraining port=9:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=48
PcieTrainPort reg=0x10000
PcieTrainPort port=0x9 result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:09.0 subordinate bus PCI Express
PCI: 00:09.0 [1022/9608] enabled
rs780_enable: dev=0002dc60, VID_DID=0x96091022
Bus-0, Dev-9, 10, Fun-0. enable=1
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0002b1b8, dev=0x0002dc60, port=0x0000000a
PcieLinkTraining port=a:lc current state=10203
PcieTrainPort port=0xa result=0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1022/9609] enabled
PCI: 00:0b.0, bad id 0xffffffff
PCI: 00:0c.0, bad id 0xffffffff
PCI: 00:0d.0, bad id 0xffffffff
PCI: 00:0e.0, bad id 0xffffffff
PCI: 00:0f.0, bad id 0xffffffff
PCI: 00:10.0, bad id 0xffffffff
sb700_enable()
PCI: 00:11.0 [1002/4390] ops
PCI: 00:11.0 [1002/4390] enabled
sb700_enable()
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb700_enable()
PCI: 00:12.1 [1002/4398] ops
PCI: 00:12.1 [1002/4398] enabled
sb700_enable()
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
PCI: 00:12.3, bad id 0xffffffff
PCI: 00:12.4, bad id 0xffffffff
PCI: 00:12.5, bad id 0xffffffff
PCI: 00:12.6, bad id 0xffffffff
PCI: 00:12.7, bad id 0xffffffff
sb700_enable()
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb700_enable()
PCI: 00:13.1 [1002/4398] ops
PCI: 00:13.1 [1002/4398] enabled
sb700_enable()
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
PCI: 00:13.3, bad id 0xffffffff
PCI: 00:13.4, bad id 0xffffffff
PCI: 00:13.5, bad id 0xffffffff
PCI: 00:13.6, bad id 0xffffffff
PCI: 00:13.7, bad id 0xffffffff
sb700_enable()
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385] enabled
sb700_enable()
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb700_enable()
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb700_enable()
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb700_enable()
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb700_enable()
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
PCI: 00:14.6, bad id 0xffffffff
PCI: 00:14.7, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0, bad id 0xffffffff
PCI: 01:01.0, bad id 0xffffffff
PCI: 01:02.0, bad id 0xffffffff
PCI: 01:03.0, bad id 0xffffffff
PCI: 01:04.0, bad id 0xffffffff
malloc Enter, size 1092, free_mem_ptr 0003c444
malloc 0003c444
PCI: 01:05.0 [1002/9615] ops
rs780_internal_gfx_enable dev = 0x0003c444, nb_dev = 0x0002b1b8.
sysmem = 0_40000000
PCI: 01:05.0 [1002/9615] enabled
PCI: 01:06.0, bad id 0xffffffff
PCI: 01:07.0, bad id 0xffffffff
PCI: 01:08.0, bad id 0xffffffff
PCI: 01:09.0, bad id 0xffffffff
PCI: 01:0a.0, bad id 0xffffffff
PCI: 01:0b.0, bad id 0xffffffff
PCI: 01:0c.0, bad id 0xffffffff
PCI: 01:0d.0, bad id 0xffffffff
PCI: 01:0e.0, bad id 0xffffffff
PCI: 01:0f.0, bad id 0xffffffff
PCI: 01:10.0, bad id 0xffffffff
PCI: 01:11.0, bad id 0xffffffff
PCI: 01:12.0, bad id 0xffffffff
PCI: 01:13.0, bad id 0xffffffff
PCI: 01:14.0, bad id 0xffffffff
PCI: 01:15.0, bad id 0xffffffff
PCI: 01:16.0, bad id 0xffffffff
PCI: 01:17.0, bad id 0xffffffff
PCI: 01:18.0, bad id 0xffffffff
PCI: 01:19.0, bad id 0xffffffff
PCI: 01:1a.0, bad id 0xffffffff
PCI: 01:1b.0, bad id 0xffffffff
PCI: 01:1c.0, bad id 0xffffffff
PCI: 01:1d.0, bad id 0xffffffff
PCI: 01:1e.0, bad id 0xffffffff
PCI: 01:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 02
PCI: 02:00.0, bad id 0xffffffff
PCI: 02:01.0, bad id 0xffffffff
PCI: 02:02.0, bad id 0xffffffff
PCI: 02:03.0, bad id 0xffffffff
PCI: 02:04.0, bad id 0xffffffff
PCI: 02:05.0, bad id 0xffffffff
PCI: 02:06.0, bad id 0xffffffff
PCI: 02:07.0, bad id 0xffffffff
PCI: 02:08.0, bad id 0xffffffff
PCI: 02:09.0, bad id 0xffffffff
PCI: 02:0a.0, bad id 0xffffffff
PCI: 02:0b.0, bad id 0xffffffff
PCI: 02:0c.0, bad id 0xffffffff
PCI: 02:0d.0, bad id 0xffffffff
PCI: 02:0e.0, bad id 0xffffffff
PCI: 02:0f.0, bad id 0xffffffff
PCI: 02:10.0, bad id 0xffffffff
PCI: 02:11.0, bad id 0xffffffff
PCI: 02:12.0, bad id 0xffffffff
PCI: 02:13.0, bad id 0xffffffff
PCI: 02:14.0, bad id 0xffffffff
PCI: 02:15.0, bad id 0xffffffff
PCI: 02:16.0, bad id 0xffffffff
PCI: 02:17.0, bad id 0xffffffff
PCI: 02:18.0, bad id 0xffffffff
PCI: 02:19.0, bad id 0xffffffff
PCI: 02:1a.0, bad id 0xffffffff
PCI: 02:1b.0, bad id 0xffffffff
PCI: 02:1c.0, bad id 0xffffffff
PCI: 02:1d.0, bad id 0xffffffff
PCI: 02:1e.0, bad id 0xffffffff
PCI: 02:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:09.0
PCI: pci_scan_bus for bus 03
malloc Enter, size 1092, free_mem_ptr 0003c888
malloc 0003c888
PCI: 03:00.0 [10ec/8168] enabled
PCI: 03:01.0, bad id 0xffffffff
PCI: 03:02.0, bad id 0xffffffff
PCI: 03:03.0, bad id 0xffffffff
PCI: 03:04.0, bad id 0xffffffff
PCI: 03:05.0, bad id 0xffffffff
PCI: 03:06.0, bad id 0xffffffff
PCI: 03:07.0, bad id 0xffffffff
PCI: 03:08.0, bad id 0xffffffff
PCI: 03:09.0, bad id 0xffffffff
PCI: 03:0a.0, bad id 0xffffffff
PCI: 03:0b.0, bad id 0xffffffff
PCI: 03:0c.0, bad id 0xffffffff
PCI: 03:0d.0, bad id 0xffffffff
PCI: 03:0e.0, bad id 0xffffffff
PCI: 03:0f.0, bad id 0xffffffff
PCI: 03:10.0, bad id 0xffffffff
PCI: 03:11.0, bad id 0xffffffff
PCI: 03:12.0, bad id 0xffffffff
PCI: 03:13.0, bad id 0xffffffff
PCI: 03:14.0, bad id 0xffffffff
PCI: 03:15.0, bad id 0xffffffff
PCI: 03:16.0, bad id 0xffffffff
PCI: 03:17.0, bad id 0xffffffff
PCI: 03:18.0, bad id 0xffffffff
PCI: 03:19.0, bad id 0xffffffff
PCI: 03:1a.0, bad id 0xffffffff
PCI: 03:1b.0, bad id 0xffffffff
PCI: 03:1c.0, bad id 0xffffffff
PCI: 03:1d.0, bad id 0xffffffff
PCI: 03:1e.0, bad id 0xffffffff
PCI: 03:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=003
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
do_pci_scan_bridge returns max 3
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 04
PCI: 04:00.0, bad id 0xffffffff
PCI: 04:01.0, bad id 0xffffffff
PCI: 04:02.0, bad id 0xffffffff
PCI: 04:03.0, bad id 0xffffffff
PCI: 04:04.0, bad id 0xffffffff
PCI: 04:05.0, bad id 0xffffffff
PCI: 04:06.0, bad id 0xffffffff
PCI: 04:07.0, bad id 0xffffffff
PCI: 04:08.0, bad id 0xffffffff
PCI: 04:09.0, bad id 0xffffffff
PCI: 04:0a.0, bad id 0xffffffff
PCI: 04:0b.0, bad id 0xffffffff
PCI: 04:0c.0, bad id 0xffffffff
PCI: 04:0d.0, bad id 0xffffffff
PCI: 04:0e.0, bad id 0xffffffff
PCI: 04:0f.0, bad id 0xffffffff
PCI: 04:10.0, bad id 0xffffffff
PCI: 04:11.0, bad id 0xffffffff
PCI: 04:12.0, bad id 0xffffffff
PCI: 04:13.0, bad id 0xffffffff
PCI: 04:14.0, bad id 0xffffffff
PCI: 04:15.0, bad id 0xffffffff
PCI: 04:16.0, bad id 0xffffffff
PCI: 04:17.0, bad id 0xffffffff
PCI: 04:18.0, bad id 0xffffffff
PCI: 04:19.0, bad id 0xffffffff
PCI: 04:1a.0, bad id 0xffffffff
PCI: 04:1b.0, bad id 0xffffffff
PCI: 04:1c.0, bad id 0xffffffff
PCI: 04:1d.0, bad id 0xffffffff
PCI: 04:1e.0, bad id 0xffffffff
PCI: 04:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=004
do_pci_scan_bridge returns max 4
scan_static_bus for PCI: 00:14.0
smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled
scan_static_bus for PCI: 00:14.0 done
scan_static_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 enabled
PNP: 002e.2 disabled
PNP: 002e.3 disabled
PNP: 002e.4 disabled
PNP: 002e.5 enabled
PNP: 002e.6 enabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
scan_static_bus for PCI: 00:14.3 done
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 05
PCI: 05:00.0, bad id 0xffffffff
PCI: 05:01.0, bad id 0xffffffff
PCI: 05:02.0, bad id 0xffffffff
PCI: 05:03.0, bad id 0xffffffff
PCI: 05:04.0, bad id 0xffffffff
PCI: 05:05.0, bad id 0xffffffff
PCI: 05:06.0, bad id 0xffffffff
PCI: 05:07.0, bad id 0xffffffff
PCI: 05:08.0, bad id 0xffffffff
PCI: 05:09.0, bad id 0xffffffff
PCI: 05:0a.0, bad id 0xffffffff
PCI: 05:0b.0, bad id 0xffffffff
PCI: 05:0c.0, bad id 0xffffffff
PCI: 05:0d.0, bad id 0xffffffff
PCI: 05:0e.0, bad id 0xffffffff
PCI: 05:0f.0, bad id 0xffffffff
PCI: 05:10.0, bad id 0xffffffff
PCI: 05:11.0, bad id 0xffffffff
PCI: 05:12.0, bad id 0xffffffff
PCI: 05:13.0, bad id 0xffffffff
PCI: 05:14.0, bad id 0xffffffff
PCI: 05:15.0, bad id 0xffffffff
PCI: 05:16.0, bad id 0xffffffff
PCI: 05:17.0, bad id 0xffffffff
PCI: 05:18.0, bad id 0xffffffff
PCI: 05:19.0, bad id 0xffffffff
PCI: 05:1a.0, bad id 0xffffffff
PCI: 05:1b.0, bad id 0xffffffff
PCI: 05:1c.0, bad id 0xffffffff
PCI: 05:1d.0, bad id 0xffffffff
PCI: 05:1e.0, bad id 0xffffffff
PCI: 05:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=005
do_pci_scan_bridge returns max 5
PCI: pci_scan_bus returning with max=005
PCI: pci_scan_bus returning with max=005
PCI_DOMAIN: 0000 passpw: enabled
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
rs780_gfx_read_resources.
PCI: 01:05.0 register 24(ffffffff), read-only ignoring it
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 2 link: 0
PCI: 00:04.0 read_resources bus 2 link: 0 done
PCI: 00:09.0 read_resources bus 3 link: 0
PCI: 00:09.0 read_resources bus 3 link: 0 done
PCI: 00:0a.0 read_resources bus 4 link: 0
PCI: 00:0a.0 read_resources bus 4 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PNP: 002e.6 missing read_resources
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 5 link: 0
PCI: 00:14.4 read_resources bus 5 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
   APIC: 01 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10
000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 inde
x 10000100
   PCI: 00:18.0 links 3 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base c00003 size 0 align 0 gran 0 limit cfff00 flags 1 index 1b0
   PCI: 00:18.0 resource base e00003 size 0 align 0 gran 0 limit efff00 flags 1 index 1b8
   PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0
   PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index
2
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1
   PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200
 index 4
    PCI: 00:00.0 links 0 child on link 0 NULL
    PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flag
s 201 index 1c
    PCI: 00:01.0 links 1 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff flags 80102 index 1c
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81202 index
 24
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 2
0
     PCI: 01:05.0 links 0 child on link 0 NULL
     PCI: 01:05.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200
index 10
     PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
     PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 inde
x 18
    PCI: 00:02.0 links 0 child on link 0 NULL
    PCI: 00:03.0 links 0 child on link 0 NULL
    PCI: 00:04.0 links 1 child on link 0 NULL
    PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1
c
    PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202
 index 24
    PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 2
0
    PCI: 00:05.0 links 0 child on link 0 NULL
    PCI: 00:06.0 links 0 child on link 0 NULL
    PCI: 00:07.0 links 0 child on link 0 NULL
    PCI: 00:08.0 links 0 child on link 0 NULL
    PCI: 00:09.0 links 1 child on link 0 PCI: 03:00.0
    PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1
c
    PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202
 index 24
    PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 2
0
     PCI: 03:00.0 links 0 child on link 0 NULL
     PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
     PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 2
01 index 18
     PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags
1201 index 20
     PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 ind
ex 30
    PCI: 00:0a.0 links 1 child on link 0 NULL
    PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1
c
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202
 index 24
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 2
0
    PCI: 00:11.0 links 0 child on link 0 NULL
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 2
4
    PCI: 00:12.0 links 0 child on link 0 NULL
    PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index
10
    PCI: 00:12.1 links 0 child on link 0 NULL
    PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index
10
    PCI: 00:12.2 links 0 child on link 0 NULL
    PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:13.0 links 0 child on link 0 NULL
    PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index
10
    PCI: 00:13.1 links 0 child on link 0 NULL
    PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index
10
    PCI: 00:13.2 links 0 child on link 0 NULL
    PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:14.0 links 1 child on link 0 I2C: 01:50
    PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags 80000
200 index 74
    PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags 80000100 index 9
0
     I2C: 01:50 links 0 child on link 0 NULL
     I2C: 01:51 links 0 child on link 0 NULL
     I2C: 01:52 links 0 child on link 0 NULL
     I2C: 01:53 links 0 child on link 0 NULL
    PCI: 00:14.1 links 0 child on link 0 NULL
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:14.2 links 0 child on link 0 NULL
    PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 20
1 index 10
    PCI: 00:14.3 links 1 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 1000
0000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 i
ndex 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 ind
ex 3
     PNP: 002e.0 links 0 child on link 0 NULL
     PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74
     PNP: 002e.1 links 0 child on link 0 NULL
     PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2 links 0 child on link 0 NULL
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
     PNP: 002e.3 links 0 child on link 0 NULL
     PNP: 002e.3 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.3 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.4 links 0 child on link 0 NULL
     PNP: 002e.5 links 0 child on link 0 NULL
     PNP: 002e.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.6 links 0 child on link 0 NULL
     PNP: 002e.6 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.7 links 0 child on link 0 NULL
     PNP: 002e.8 links 0 child on link 0 NULL
     PNP: 002e.8 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.8 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.9 links 0 child on link 0 NULL
     PNP: 002e.9 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.a links 0 child on link 0 NULL
    PCI: 00:14.4 links 1 child on link 0 NULL
    PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
    PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 2
4
    PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 2
0
    PCI: 00:14.5 links 0 child on link 0 NULL
    PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index
10
   PCI: 00:18.1 links 0 child on link 0 NULL
   PCI: 00:18.2 links 0 child on link 0 NULL
   PCI: 00:18.3 links 0 child on link 0 NULL
   PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 inde
x 94
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff
PCI: 01:05.0 14 *  [0x0 - 0xff] io
PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:00.0 10 *  [0x0 - 0xff] io
PCI: 00:09.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c *  [0x0 - 0xfff] io
PCI: 00:09.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:11.0 20 *  [0x2000 - 0x200f] io
PCI: 00:14.1 20 *  [0x2010 - 0x201f] io
PCI: 00:11.0 10 *  [0x2020 - 0x2027] io
PCI: 00:11.0 18 *  [0x2028 - 0x202f] io
PCI: 00:14.1 10 *  [0x2030 - 0x2037] io
PCI: 00:14.1 18 *  [0x2038 - 0x203f] io
PCI: 00:11.0 14 *  [0x2040 - 0x2043] io
PCI: 00:11.0 1c *  [0x2044 - 0x2047] io
PCI: 00:14.1 14 *  [0x2048 - 0x204b] io
PCI: 00:14.1 1c *  [0x204c - 0x204f] io
PCI: 00:18.0 compute_resources_io: base: 2050 size: 3000 align: 12 gran: 12 limit: ffff don
e
PCI: 00:18.0 00 *  [0x0 - 0x2fff] io
PCI_DOMAIN: 0000 compute_resources_io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff
done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
f
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
f
PCI: 01:05.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 li
mit: ffffffff done
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
fffffff
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
fffffff done
PCI: 00:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
fffffff
PCI: 03:00.0 20 *  [0x0 - 0xffff] prefmem
PCI: 00:09.0 compute_resources_prefmem: base: 10000 size: 100000 align: 20 gran: 20 limit:
ffffffffffffffff done
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
fffffff
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
fffffff done
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
done
PCI: 00:01.0 24 *  [0x0 - 0xfffffff] prefmem
PCI: 00:09.0 24 *  [0x10000000 - 0x100fffff] prefmem
PCI: 00:18.0 compute_resources_prefmem: base: 10100000 size: 10100000 align: 28 gran: 20 li
mit: ffffffff done
PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 18 *  [0x0 - 0xffff] mem
PCI: 00:01.0 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffff
ffff done
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:09.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.0 30 *  [0x0 - 0x1ffff] mem
PCI: 03:00.0 18 *  [0x20000 - 0x20fff] mem
PCI: 00:09.0 compute_resources_mem: base: 21000 size: 100000 align: 20 gran: 20 limit: ffff
ffff done
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:00.0 1c *  [0x0 - 0xfffffff] mem
PCI: 00:01.0 20 *  [0x10000000 - 0x100fffff] mem
PCI: 00:09.0 20 *  [0x10100000 - 0x101fffff] mem
PCI: 00:14.2 10 *  [0x10200000 - 0x10203fff] mem
PCI: 00:12.0 10 *  [0x10204000 - 0x10204fff] mem
PCI: 00:12.1 10 *  [0x10205000 - 0x10205fff] mem
PCI: 00:13.0 10 *  [0x10206000 - 0x10206fff] mem
PCI: 00:13.1 10 *  [0x10207000 - 0x10207fff] mem
PCI: 00:14.5 10 *  [0x10208000 - 0x10208fff] mem
PCI: 00:11.0 24 *  [0x10209000 - 0x102093ff] mem
PCI: 00:12.2 10 *  [0x10209400 - 0x102094ff] mem
PCI: 00:13.2 10 *  [0x10209500 - 0x102095ff] mem
PCI: 00:14.3 a0 *  [0x10209600 - 0x10209600] mem
PCI: 00:18.0 compute_resources_mem: base: 10209601 size: 10300000 align: 28 gran: 20 limit:
 ffffffff done
PCI: 00:18.0 01 *  [0x0 - 0x102fffff] mem
PCI: 00:18.0 02 *  [0x20000000 - 0x300fffff] prefmem
PCI: 00:18.3 94 *  [0x34000000 - 0x37ffffff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 38000000 size: 38000000 align: 28 gran: 0 lim
it: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 01:05.0
constrain_resources: PCI: 00:04.0
constrain_resources: PCI: 00:09.0
constrain_resources: PCI: 03:00.0
constrain_resources: PCI: 00:0a.0
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:12.1
constrain_resources: PCI: 00:12.2
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:13.1
constrain_resources: PCI: 00:13.2
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 01:50
constrain_resources: I2C: 01:51
constrain_resources: I2C: 01:52
constrain_resources: I2C: 01:53
constrain_resources: PCI: 00:14.1
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PNP: 002e.1
constrain_resources: PNP: 002e.5
constrain_resources: PNP: 002e.6
skipping PNP: 002e.6@70 fixed resource, size=0!
constrain_resources: PCI: 00:14.4
constrain_resources: PCI: 00:14.5
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
        lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
        lim->base 000c0000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:3000 align:12 gran:0 limit:ffff
Assigned: PCI: 00:18.0 00 *  [0x1000 - 0x3fff] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 4000 size: 3000 align: 12 gran: 0 done
PCI: 00:18.0 allocate_resources_io: base:1000 size:3000 align:12 gran:12 limit:ffff
Assigned: PCI: 00:01.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:09.0 1c *  [0x2000 - 0x2fff] io
Assigned: PCI: 00:11.0 20 *  [0x3000 - 0x300f] io
Assigned: PCI: 00:14.1 20 *  [0x3010 - 0x301f] io
Assigned: PCI: 00:11.0 10 *  [0x3020 - 0x3027] io
Assigned: PCI: 00:11.0 18 *  [0x3028 - 0x302f] io
Assigned: PCI: 00:14.1 10 *  [0x3030 - 0x3037] io
Assigned: PCI: 00:14.1 18 *  [0x3038 - 0x303f] io
Assigned: PCI: 00:11.0 14 *  [0x3040 - 0x3043] io
Assigned: PCI: 00:11.0 1c *  [0x3044 - 0x3047] io
Assigned: PCI: 00:14.1 14 *  [0x3048 - 0x304b] io
Assigned: PCI: 00:14.1 1c *  [0x304c - 0x304f] io
PCI: 00:18.0 allocate_resources_io: next_base: 3050 size: 3000 align: 12 gran: 12 done
PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:05.0 14 *  [0x1000 - 0x10ff] io
PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI: 00:04.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:04.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:09.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 03:00.0 10 *  [0x2000 - 0x20ff] io
PCI: 00:09.0 allocate_resources_io: next_base: 2100 size: 1000 align: 12 gran: 12 done
PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:38000000 align:28 gran:0 limit:
febfffff
Assigned: PCI: 00:18.0 01 *  [0xc0000000 - 0xd02fffff] mem
Assigned: PCI: 00:18.0 02 *  [0xe0000000 - 0xf00fffff] prefmem
Assigned: PCI: 00:18.3 94 *  [0xf4000000 - 0xf7ffffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f8000000 size: 38000000 align: 28 gran:
 0 done
PCI: 00:18.0 allocate_resources_prefmem: base:e0000000 size:10100000 align:28 gran:20 limit
:febfffff
Assigned: PCI: 00:01.0 24 *  [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:09.0 24 *  [0xf0000000 - 0xf00fffff] prefmem
PCI: 00:18.0 allocate_resources_prefmem: next_base: f0100000 size: 10100000 align: 28 gran:
 20 done
PCI: 00:01.0 allocate_resources_prefmem: base:e0000000 size:10000000 align:28 gran:20 limit
:febfffff
Assigned: PCI: 01:05.0 10 *  [0xe0000000 - 0xefffffff] prefmem
PCI: 00:01.0 allocate_resources_prefmem: next_base: f0000000 size: 10000000 align: 28 gran:
 20 done
PCI: 00:04.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfff
ff
PCI: 00:04.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 don
e
PCI: 00:09.0 allocate_resources_prefmem: base:f0000000 size:100000 align:20 gran:20 limit:f
ebfffff
Assigned: PCI: 03:00.0 20 *  [0xf0000000 - 0xf000ffff] prefmem
PCI: 00:09.0 allocate_resources_prefmem: next_base: f0010000 size: 100000 align: 20 gran: 2
0 done
PCI: 00:0a.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfff
ff
PCI: 00:0a.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 don
e
PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfff
ff
PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 don
e
PCI: 00:18.0 allocate_resources_mem: base:c0000000 size:10300000 align:28 gran:20 limit:feb
fffff
Assigned: PCI: 00:00.0 1c *  [0xc0000000 - 0xcfffffff] mem
Assigned: PCI: 00:01.0 20 *  [0xd0000000 - 0xd00fffff] mem
Assigned: PCI: 00:09.0 20 *  [0xd0100000 - 0xd01fffff] mem
Assigned: PCI: 00:14.2 10 *  [0xd0200000 - 0xd0203fff] mem
Assigned: PCI: 00:12.0 10 *  [0xd0204000 - 0xd0204fff] mem
Assigned: PCI: 00:12.1 10 *  [0xd0205000 - 0xd0205fff] mem
Assigned: PCI: 00:13.0 10 *  [0xd0206000 - 0xd0206fff] mem
Assigned: PCI: 00:13.1 10 *  [0xd0207000 - 0xd0207fff] mem
Assigned: PCI: 00:14.5 10 *  [0xd0208000 - 0xd0208fff] mem
Assigned: PCI: 00:11.0 24 *  [0xd0209000 - 0xd02093ff] mem
Assigned: PCI: 00:12.2 10 *  [0xd0209400 - 0xd02094ff] mem
Assigned: PCI: 00:13.2 10 *  [0xd0209500 - 0xd02095ff] mem
Assigned: PCI: 00:14.3 a0 *  [0xd0209600 - 0xd0209600] mem
PCI: 00:18.0 allocate_resources_mem: next_base: d0209601 size: 10300000 align: 28 gran: 20
done
PCI: 00:01.0 allocate_resources_mem: base:d0000000 size:100000 align:20 gran:20 limit:febff
fff
Assigned: PCI: 01:05.0 18 *  [0xd0000000 - 0xd000ffff] mem
PCI: 00:01.0 allocate_resources_mem: next_base: d0010000 size: 100000 align: 20 gran: 20 do
ne
PCI: 00:04.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:04.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:09.0 allocate_resources_mem: base:d0100000 size:100000 align:20 gran:20 limit:febff
fff
Assigned: PCI: 03:00.0 30 *  [0xd0100000 - 0xd011ffff] mem
Assigned: PCI: 03:00.0 18 *  [0xd0120000 - 0xd0120fff] mem
PCI: 00:09.0 allocate_resources_mem: next_base: d0121000 size: 100000 align: 20 gran: 20 do
ne
PCI: 00:0a.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:0a.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
node 0 : uma_memory_base/1024=0x000c0000, mmio_basek=0x00000000, basek=0x00300000, limitk=0
x00000300
node 0: UMA memory starts below mmio_basek
0: mmio_basek=00300000, basek=00000300, limitk=00100000
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0
PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io <node 0 link
 0>
PCI: 00:18.0 1b0 <- [0x00e0000000 - 0x00f00fffff] size 0x10100000 gran 0x14 prefmem <node 0
 link 0>
PCI: 00:18.0 1b8 <- [0x00c0000000 - 0x00d02fffff] size 0x10300000 gran 0x14 mem <node 0 lin
k 0>
PCI: 00:18.0 1a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 lin
k 0>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:00.0 1c <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c mem64
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00d0000000 - 0x00d00fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:05.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PCI: 01:05.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:05.0 18 <- [0x00d0000000 - 0x00d000ffff] size 0x00010000 gran 0x10 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:04.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:04.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:04.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:09.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:09.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 03 prefmem
PCI: 00:09.0 20 <- [0x00d0100000 - 0x00d01fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 03:00.0 18 <- [0x00d0120000 - 0x00d0120fff] size 0x00001000 gran 0x0c mem64
PCI: 03:00.0 20 <- [0x00f0000000 - 0x00f000ffff] size 0x00010000 gran 0x10 prefmem64
PCI: 03:00.0 30 <- [0x00d0100000 - 0x00d011ffff] size 0x00020000 gran 0x11 romem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
PCI: 00:0a.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:0a.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 mem
PCI: 00:11.0 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000003040 - 0x0000003043] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000003028 - 0x000000302f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000003044 - 0x0000003047] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000003000 - 0x000000300f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00d0209000 - 0x00d02093ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00d0204000 - 0x00d0204fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.1 10 <- [0x00d0205000 - 0x00d0205fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00d0209400 - 0x00d02094ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00d0206000 - 0x00d0206fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.1 10 <- [0x00d0207000 - 0x00d0207fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00d0209500 - 0x00d02095ff] size 0x00000100 gran 0x08 mem
ERROR: PCI: 00:14.0 74 mem size: 0x0000001000 not assigned
ERROR: PCI: 00:14.0 90 io size: 0x0000000010 not assigned
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.1 10 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000003048 - 0x000000304b] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000003038 - 0x000000303f] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x000000304c - 0x000000304f] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000003010 - 0x000000301f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00d0200000 - 0x00d0203fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00d0209600 - 0x00d0209600] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io
PNP: 002e.5 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran 0x03 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.6 missing set_resources
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 mem
PCI: 00:14.5 10 <- [0x00d0208000 - 0x00d0208fff] size 0x00001000 gran 0x0c mem
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
   APIC: 01 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 i
ndex 10000000
  PCI_DOMAIN: 0000 resource base c0000000 size 38000000 align 28 gran 0 limit febfffff flag
s 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 1
0
  PCI_DOMAIN: 0000 resource base c0000 size 3ff40000 align 0 gran 0 limit 0 flags e0004200
index 20
   PCI: 00:18.0 links 3 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit ffff flags 60080100 ind
ex 1c0
   PCI: 00:18.0 resource base e0000000 size 10100000 align 28 gran 20 limit febfffff flags
60081200 index 1b0
   PCI: 00:18.0 resource base c0000000 size 10300000 align 28 gran 20 limit febfffff flags
60080200 index 1b8
   PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200
 index 1a8
    PCI: 00:00.0 links 0 child on link 0 NULL
    PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit febfffff flags
 60000201 index 1c
    PCI: 00:01.0 links 1 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 in
dex 1c
    PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 20 limit febfffff flags
 60081202 index 24
    PCI: 00:01.0 resource base d0000000 size 100000 align 20 gran 20 limit febfffff flags 6
0080202 index 20
     PCI: 01:05.0 links 0 child on link 0 NULL
     PCI: 01:05.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flag
s 60001200 index 10
     PCI: 01:05.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 inde
x 14
     PCI: 01:05.0 resource base d0000000 size 10000 align 16 gran 16 limit febfffff flags 6
0000200 index 18
    PCI: 00:02.0 links 0 child on link 0 NULL
    PCI: 00:03.0 links 0 child on link 0 NULL
    PCI: 00:04.0 links 1 child on link 0 NULL
    PCI: 00:04.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index
 1c
    PCI: 00:04.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 600812
02 index 24
    PCI: 00:04.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 600802
02 index 20
    PCI: 00:05.0 links 0 child on link 0 NULL
    PCI: 00:06.0 links 0 child on link 0 NULL
    PCI: 00:07.0 links 0 child on link 0 NULL
    PCI: 00:08.0 links 0 child on link 0 NULL
    PCI: 00:09.0 links 1 child on link 0 PCI: 03:00.0
    PCI: 00:09.0 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 in
dex 1c
    PCI: 00:09.0 resource base f0000000 size 100000 align 20 gran 20 limit febfffff flags 6
0081202 index 24
    PCI: 00:09.0 resource base d0100000 size 100000 align 20 gran 20 limit febfffff flags 6
0080202 index 20
     PCI: 03:00.0 links 0 child on link 0 NULL
     PCI: 03:00.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 inde
x 10
     PCI: 03:00.0 resource base d0120000 size 1000 align 12 gran 12 limit febfffff flags 60
000201 index 18
     PCI: 03:00.0 resource base f0000000 size 10000 align 16 gran 16 limit febfffff flags 6
0001201 index 20
     PCI: 03:00.0 resource base d0100000 size 20000 align 17 gran 17 limit febfffff flags 6
0002200 index 30
    PCI: 00:0a.0 links 1 child on link 0 NULL
    PCI: 00:0a.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index
 1c
    PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 600812
02 index 24
    PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 600802
02 index 20
    PCI: 00:11.0 links 0 child on link 0 NULL
    PCI: 00:11.0 resource base 3020 size 8 align 3 gran 3 limit ffff flags 60000100 index 1
0
    PCI: 00:11.0 resource base 3040 size 4 align 2 gran 2 limit ffff flags 60000100 index 1
4
    PCI: 00:11.0 resource base 3028 size 8 align 3 gran 3 limit ffff flags 60000100 index 1
8
    PCI: 00:11.0 resource base 3044 size 4 align 2 gran 2 limit ffff flags 60000100 index 1
c
    PCI: 00:11.0 resource base 3000 size 10 align 4 gran 4 limit ffff flags 60000100 index
20
    PCI: 00:11.0 resource base d0209000 size 400 align 10 gran 10 limit febfffff flags 6000
0200 index 24
    PCI: 00:12.0 links 0 child on link 0 NULL
    PCI: 00:12.0 resource base d0204000 size 1000 align 12 gran 12 limit febfffff flags 600
00200 index 10
    PCI: 00:12.1 links 0 child on link 0 NULL
    PCI: 00:12.1 resource base d0205000 size 1000 align 12 gran 12 limit febfffff flags 600
00200 index 10
    PCI: 00:12.2 links 0 child on link 0 NULL
    PCI: 00:12.2 resource base d0209400 size 100 align 8 gran 8 limit febfffff flags 600002
00 index 10
    PCI: 00:13.0 links 0 child on link 0 NULL
    PCI: 00:13.0 resource base d0206000 size 1000 align 12 gran 12 limit febfffff flags 600
00200 index 10
    PCI: 00:13.1 links 0 child on link 0 NULL
    PCI: 00:13.1 resource base d0207000 size 1000 align 12 gran 12 limit febfffff flags 600
00200 index 10
    PCI: 00:13.2 links 0 child on link 0 NULL
    PCI: 00:13.2 resource base d0209500 size 100 align 8 gran 8 limit febfffff flags 600002
00 index 10
    PCI: 00:14.0 links 1 child on link 0 I2C: 01:50
    PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags 80000
200 index 74
    PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags 80000100 index 9
0
     I2C: 01:50 links 0 child on link 0 NULL
     I2C: 01:51 links 0 child on link 0 NULL
     I2C: 01:52 links 0 child on link 0 NULL
     I2C: 01:53 links 0 child on link 0 NULL
    PCI: 00:14.1 links 0 child on link 0 NULL
    PCI: 00:14.1 resource base 3030 size 8 align 3 gran 3 limit ffff flags 60000100 index 1
0
    PCI: 00:14.1 resource base 3048 size 4 align 2 gran 2 limit ffff flags 60000100 index 1
4
    PCI: 00:14.1 resource base 3038 size 8 align 3 gran 3 limit ffff flags 60000100 index 1
8
    PCI: 00:14.1 resource base 304c size 4 align 2 gran 2 limit ffff flags 60000100 index 1
c
    PCI: 00:14.1 resource base 3010 size 10 align 4 gran 4 limit ffff flags 60000100 index
20
    PCI: 00:14.2 links 0 child on link 0 NULL
    PCI: 00:14.2 resource base d0200000 size 4000 align 14 gran 14 limit febfffff flags 600
00201 index 10
    PCI: 00:14.3 links 1 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base d0209600 size 1 align 0 gran 0 limit febfffff flags 60000200
 index a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 1000
0000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 i
ndex 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 ind
ex 3
     PNP: 002e.0 links 0 child on link 0 NULL
     PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74
     PNP: 002e.1 links 0 child on link 0 NULL
     PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
     PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.2 links 0 child on link 0 NULL
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
     PNP: 002e.3 links 0 child on link 0 NULL
     PNP: 002e.3 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.3 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.4 links 0 child on link 0 NULL
     PNP: 002e.5 links 0 child on link 0 NULL
     PNP: 002e.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
     PNP: 002e.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.6 links 0 child on link 0 NULL
     PNP: 002e.6 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.7 links 0 child on link 0 NULL
     PNP: 002e.8 links 0 child on link 0 NULL
     PNP: 002e.8 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.8 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.9 links 0 child on link 0 NULL
     PNP: 002e.9 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
     PNP: 002e.a links 0 child on link 0 NULL
    PCI: 00:14.4 links 1 child on link 0 NULL
    PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index
 1c
    PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 600812
02 index 24
    PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 600802
02 index 20
    PCI: 00:14.5 links 0 child on link 0 NULL
    PCI: 00:14.5 resource base d0208000 size 1000 align 12 gran 12 limit febfffff flags 600
00200 index 10
   PCI: 00:18.1 links 0 child on link 0 NULL
   PCI: 00:18.2 links 0 child on link 0 NULL
   PCI: 00:18.3 links 0 child on link 0 NULL
   PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit febfffff flags 6
0000200 index 94
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:00.0 subsystem <- 1022/3060
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 07
PCI: 01:05.0 cmd <- 03
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 00
PCI: 00:09.0 bridge ctrl <- 0003
PCI: 00:09.0 cmd <- 07
PCI: 03:00.0 cmd <- 03
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 00
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1022/3060
PCI: 00:12.0 cmd <- 02
PCI: 00:12.1 subsystem <- 1022/3060
PCI: 00:12.1 cmd <- 02
PCI: 00:12.2 subsystem <- 1022/3060
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1022/3060
PCI: 00:13.0 cmd <- 02
PCI: 00:13.1 subsystem <- 1022/3060
PCI: 00:13.1 cmd <- 02
PCI: 00:13.2 subsystem <- 1022/3060
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1022/3060
PCI: 00:14.0 cmd <- 403
PCI: 00:14.1 subsystem <- 1022/3060
PCI: 00:14.1 cmd <- 01
PCI: 00:14.2 subsystem <- 1022/3060
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1022/3060
PCI: 00:14.3 cmd <- 0f
sb700 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff
sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000067
sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x0000006b
PNP: 002e.6 missing enable_resources
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 cmd <- 01
PCI: 00:14.5 subsystem <- 1022/3060
PCI: 00:14.5 cmd <- 02
PCI: 00:18.1 subsystem <- 1022/3060
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/3060
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor AMD device 60fb2
CPU: family 0f, model 6b, stepping 02
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 1024MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 1, base: 1024MB, range:  256MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 2, base:  768MB, range:  256MB, type UC
ADDRESS_MASK_HIGH=0xff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 4200+
Setting up local apic... apic_id: 0x00 done.
ECC Disabled
CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Initializing CPU #1
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 60fb2
Sending STARTUP #2 to 1.
After apic_write.
CPU: family 0f, model 6b, stepping 02
Startup point 1.
Waiting for send to finish...
+Enabling cache
After Startup.
Waiting for 1 CPUS to stop

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 1024MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 1, base: 1024MB, range:  256MB, type WB
ADDRESS_MASK_HIGH=0xff
Setting variable MTRR 2, base:  768MB, range:  256MB, type UC
ADDRESS_MASK_HIGH=0xff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 4200+
Setting up local apic... apic_id: 0x01 done.
CPU #1 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:00.0 init
pcie_init in rs780_ht.c
PCI: 00:11.0 init
sata_bar0=3020
sata_bar1=3040
sata_bar2=3028
sata_bar3=3044
sata_bar4=3000
sata_bar5=d0209000
SATA port 0 status = 0
No Primary Master SATA drive on Slot0
SATA port 1 status = 0
No Primary Slave SATA drive on Slot1
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3
PCI: 00:12.0 init
PCI: 00:12.1 init
PCI: 00:12.2 init
usb2_bar0=d0209400
PCI: 00:13.0 init
PCI: 00:13.1 init
PCI: 00:13.2 init
usb2_bar0=d0209500
PCI: 00:14.0 init
sm_init().
lapicid = 0000000000000000
set power on after power fail
++++++++++no set NMI+++++
RTC Init
sm_init() end
PCI: 00:14.1 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11c78 + align -> fff27780
Check fallback/payload
CBFS: follow chain: fff27780 + 38 + 15a68 + align -> fff3d240
Check fallback/coreboot_ram
CBFS: follow chain: fff3d240 + 38 + 11c69 + align -> fff4ef00
Check pci1002,9615.rom
CBFS: follow chain: fff4ef00 + 38 + ec00 + align -> fff5db40
Check
CBFS: follow chain: fff5db40 + 28 + 72478 + align -> fffd0000
CBFS:  Could not find file pci1002,439c.rom
PCI: 00:14.2 init
base = d0200000
codec_mask = 01
codec viddid: 10ec0888
Dev=PCI: 00:14.2
Default viddid=10ec0882
Reading viddid=10ec0888
No verb!
PCI: 00:14.3 init
PNP: 002e.1 init
PNP: 002e.5 init
Keyboard init...
Keyboard selftest failed ACK: 0xfe
PCI: 00:14.4 init
PCI: 00:14.5 init
PCI: 00:18.1 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11c78 + align -> fff27780
Check fallback/payload
CBFS: follow chain: fff27780 + 38 + 15a68 + align -> fff3d240
Check fallback/coreboot_ram
CBFS: follow chain: fff3d240 + 38 + 11c69 + align -> fff4ef00
Check pci1002,9615.rom
CBFS: follow chain: fff4ef00 + 38 + ec00 + align -> fff5db40
Check
CBFS: follow chain: fff5db40 + 28 + 72478 + align -> fffd0000
CBFS:  Could not find file pci1022,1101.rom
PCI: 00:18.2 init
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11c78 + align -> fff27780
Check fallback/payload
CBFS: follow chain: fff27780 + 38 + 15a68 + align -> fff3d240
Check fallback/coreboot_ram
CBFS: follow chain: fff3d240 + 38 + 11c69 + align -> fff4ef00
Check pci1002,9615.rom
CBFS: follow chain: fff4ef00 + 38 + ec00 + align -> fff5db40
Check
CBFS: follow chain: fff5db40 + 28 + 72478 + align -> fffd0000
CBFS:  Could not find file pci1022,1102.rom
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 01:05.0 init
internal_gfx_pci_dev_init device=9615, vendor=1002.
MEMCLK = 3
NB HT speed = 1c750660.
CPU HT speed = 80750622.
HT width = 11110020.
Check CBFS header at fffcffe0
magic is 4f524243
Found CBFS header at fffcffe0
Check normal/payload
CBFS: follow chain: fff00000 + 28 + 15a68 + align -> fff15ac0
Check normal/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 11c78 + align -> fff27780
Check fallback/payload
CBFS: follow chain: fff27780 + 38 + 15a68 + align -> fff3d240
Check fallback/coreboot_ram
CBFS: follow chain: fff3d240 + 38 + 11c69 + align -> fff4ef00
Check pci1002,9615.rom
In cbfs, rom address for PCI: 01:05.0 = fff4ef38
PCI Expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x01c0
PCI ROM Image, Vendor 1002, Device 9615,
PCI ROM Image,  Class Code 030000, Code Type 00
copying VGA ROM Image from fff4ef38 to 0xc0000, 0xec00 bytes
Executing Initialization Vector...
Myles Watson - 2009-11-24 16:09:41
Zheng,

From the K8 log:

PCI: 00:02.0: enabled 0, 0 resources
PCI: 00:03.0: enabled 0, 0 resources

These devices are enabled for fam10, but disabled for the K8 board.  I
thought the only difference was supposed to be the processor/northbridge.

Because of that, rs780_gfx_init doesn't get run.  UMA is also different.

I'm not sure what's actually breaking it, but it would be easier to tell if
you minimize some of those differences.

Thanks,
Myles
Bao, Zheng - 2009-11-25 07:34:01
These devices used to be enabled. I just disabled when the internal gfx
hanged. I tried again with those enabled, the log is not much different
except the message printed in rs780_gfx_init.


Zheng

-----Original Message-----
From: Myles Watson [mailto:mylesgw@gmail.com] 
Sent: Wednesday, November 25, 2009 12:10 AM
To: Bao, Zheng
Cc: 'coreboot'
Subject: RE: [coreboot] [v2] r4925 makes my linux hang

Zheng,

From the K8 log:

PCI: 00:02.0: enabled 0, 0 resources
PCI: 00:03.0: enabled 0, 0 resources

These devices are enabled for fam10, but disabled for the K8 board.  I
thought the only difference was supposed to be the
processor/northbridge.

Because of that, rs780_gfx_init doesn't get run.  UMA is also different.

I'm not sure what's actually breaking it, but it would be easier to tell
if
you minimize some of those differences.

Thanks,
Myles
Myles Watson - 2009-11-25 14:08:30
Since I don't have the hardware, I only have the log files to look at.
Could you send a working log file with the onboard patch and the broken one
without it?  That way the only differences should be related to that change.

Thanks,
Myles
Bao, Zheng - 2009-11-26 02:08:50
I could not narrow down the difference to a minimum scale. When I
started merge my code to the official code, it kept not working for a
long time. So the latest working code has to be got from my own
repository, which doesn't have CBFS support. Please see if it is help.


Zheng

-----Original Message-----
From: coreboot-bounces+zheng.bao=amd.com@coreboot.org
[mailto:coreboot-bounces+zheng.bao=amd.com@coreboot.org] On Behalf Of
Myles Watson
Sent: Wednesday, November 25, 2009 10:09 PM
To: Bao, Zheng
Cc: 'coreboot'
Subject: Re: [coreboot] [v2] r4925 makes my linux hang

Since I don't have the hardware, I only have the log files to look at.
Could you send a working log file with the onboard patch and the broken
one
without it?  That way the only differences should be related to that
change.

Thanks,
Myles

Patch

===================================================================
--- trunk/src/devices/pci_rom.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/devices/pci_rom.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -31,42 +31,37 @@ 
 
 struct rom_header * pci_rom_probe(struct device *dev)
 {
-	unsigned long rom_address = 0;
 	struct rom_header *rom_header;
 	struct pci_data *rom_data;
 
-	void *v;
-	/* if it's in FLASH, then it's as if dev->on_mainboard was true
*/
-	v = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
-	printk_debug("In cbfs, rom address for %s = %p\n", 
-			dev_path(dev), v);
-	if (v) {
-		dev->rom_address = (u32)v;
-		dev->on_mainboard = 1;
-	}
+	/* If it's in FLASH, then don't check device for ROM. */
+	rom_header = cbfs_load_optionrom(dev->vendor, dev->device,
NULL);
 
-	if (dev->on_mainboard) {
-                // in case some device PCI_ROM_ADDRESS can not be set
or readonly 
-		rom_address = dev->rom_address;
-		printk_debug("On mainboard, rom address for %s = %lx\n",

-			dev_path(dev), rom_address);
+	if (rom_header) {
+		printk_debug("In cbfs, rom address for %s = %p\n",
+			     dev_path(dev), rom_header);
 	} else {
+		unsigned long rom_address;
+
 		rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
-		printk_debug("On card, rom address for %s = %lx\n", 
-				dev_path(dev), rom_address);
-	}
 
-	if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
-		return NULL;
-	}
+		if (rom_address == 0x00000000 || rom_address ==
0xffffffff) {
+			#if CONFIG_BOARD_EMULATION_QEMU_X86
+			rom_address = 0xc0000;
+			#else
+			return NULL;
+			#endif
+		} else {
+			/* enable expansion ROM address decoding */
+			pci_write_config32(dev, PCI_ROM_ADDRESS,
+
rom_address|PCI_ROM_ADDRESS_ENABLE);
+		}
 
-	if(!dev->on_mainboard) {
-		/* enable expansion ROM address decoding */
-		pci_write_config32(dev, PCI_ROM_ADDRESS,
-				   rom_address|PCI_ROM_ADDRESS_ENABLE);
+		printk_debug("On card, rom address for %s = %lx\n",
+				dev_path(dev), rom_address);