Submitter | Libra Li |
---|---|
Date | 2009-11-24 03:22:41 |
Message ID | <df21912a0911231922h60b0224br526222db7131bb60@mail.gmail.com> |
Download | mbox | patch |
Permalink | /patch/586/ |
State | Superseded |
Headers | show |
Comments
Hi, Libra, Do the definitions of PMIO apply to all the chipset? +void speaker_timer_on(void) +{ + /* Setting this bit will configure GPIO to be speaker output */ +#ifndef EARLY_STAGE + pm_iowrite(0x60, (pmio_read(0x60) | (1<<5))); +#else + pmio_write(0x60, (pmio_read(0x60) | (1<<5))); +#endif // EARLY_STAGE + outb((inb(PPC_PORTB) | PPCB_SPKR), PPC_PORTB); +} + +void speaker_timer_off(void) +{ + outb((inb(PPC_PORTB) & ~PPCB_SPKR), PPC_PORTB); +} + Zheng
Hi, Bao, I'm sorry. I cancel it. Thanks. 2009/11/24 Bao, Zheng <Zheng.Bao@amd.com> > Hi, Libra, > > > > Do the definitions of PMIO apply to all the chipset? > > > > +void speaker_timer_on(void) > > +{ > > + /* Setting this bit will configure GPIO to be speaker output */ > > +#ifndef EARLY_STAGE > > + pm_iowrite(0x60, (pmio_read(0x60) | (1<<5))); > > +#else > > + pmio_write(0x60, (pmio_read(0x60) | (1<<5))); > > +#endif // EARLY_STAGE > > + outb((inb(PPC_PORTB) | PPCB_SPKR), PPC_PORTB); > > +} > > + > > +void speaker_timer_off(void) > > +{ > > + outb((inb(PPC_PORTB) & ~PPCB_SPKR), PPC_PORTB); > > +} > > + > > > > > > > > Zheng > > > ------------------------------ > > *From:* coreboot-bounces@coreboot.org [mailto: > coreboot-bounces@coreboot.org] *On Behalf Of *Libra Li > *Sent:* Tuesday, November 24, 2009 11:23 AM > *To:* coreboot > *Subject:* [coreboot] [PATCH] The PC buzzer > > > > Hi, > > This function tried in the SB600. > I had little modification "src/pc80/i8254.c". > Thanks > > Signed-off: Libra Li <libra.li@technexion.com> > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >
Patch
Index: src/mainboard/technexion/tim5690/cache_as_ram_auto.c =================================================================== --- src/mainboard/technexion/tim5690/cache_as_ram_auto.c (revision 4952) +++ src/mainboard/technexion/tim5690/cache_as_ram_auto.c (working copy) @@ -103,7 +103,11 @@ #define TECHNEXION_EARLY_SETUP #include "tn_post_code.c" +#define EARLY_STAGE +#define CONFIG_UDELAY_TIMER2 +#include "pc80/i8254.c" + #if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -249,6 +253,9 @@ soft_reset(); } + load_timer2(TICKS_PER_MS); + speaker_timer_on(); + allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now; */ @@ -261,6 +268,8 @@ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + speaker_timer_off(); + rs690_before_pci_init(); sb600_before_pci_init(); Index: src/pc80/i8254.c =================================================================== --- src/pc80/i8254.c (revision 4952) +++ src/pc80/i8254.c (working copy) @@ -17,10 +17,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef EARLY_STAGE + #include <arch/io.h> #include <pc80/i8254.h> #include <console/console.h> +#else + +#include <pc80/i8254.h> + +#endif // EARLY_STAGE + /* Initialize i8254 timers */ void setup_i8254(void) @@ -45,11 +53,30 @@ outb(ticks >> 8, TIMER2_PORT); } - +#ifndef EARLY_STAGE void udelay(int usecs) { load_timer2((usecs*TICKS_PER_MS)/1000); while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0) ; } -#endif +#endif // EARLY_STAGE + +/* This function is working after load_timer2() function. */ +void speaker_timer_on(void) +{ + /* Setting this bit will configure GPIO to be speaker output */ +#ifndef EARLY_STAGE + pm_iowrite(0x60, (pmio_read(0x60) | (1<<5))); +#else + pmio_write(0x60, (pmio_read(0x60) | (1<<5))); +#endif // EARLY_STAGE + outb((inb(PPC_PORTB) | PPCB_SPKR), PPC_PORTB); +} + +void speaker_timer_off(void) +{ + outb((inb(PPC_PORTB) & ~PPCB_SPKR), PPC_PORTB); +} + +#endif // CONFIG_UDELAY_TIMER2