===================================================================
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+void speaker_init(uint8_t time);
+void speaker_on_nodelay(void);
+void speaker_off_nodelay(void);
+void speaker_on_delay(void);
+void speaker_off_delay(void);
===================================================================
@@ -32,6 +32,8 @@
# This is debug message for products of Technexion.
obj-y += tn_post_code.o
+obj-y += speaker.o
+
# This is part of the conversion to init-obj and away from included code.
initobj-y += crt0.o
===================================================================
@@ -100,8 +100,8 @@
#include "cpu/amd/model_fxx/fidvid.c"
-#define TECHNEXION_EARLY_SETUP
#include "tn_post_code.c"
+#include "speaker.c"
#if CONFIG_USE_FALLBACK_IMAGE == 1
@@ -249,6 +249,9 @@
soft_reset();
}
+ speaker_init(255);
+ speaker_on_nodelay();
+
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
@@ -261,6 +264,8 @@
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+ speaker_off_nodelay();
+
rs690_before_pci_init();
sb600_before_pci_init();
===================================================================
@@ -1,6 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
-#ifdef TECHNEXION_EARLY_SETUP
+#ifdef __PRE_RAM__
+
#include <arch/cpu.h>
#include "southbridge/amd/sb600/sb600.h"
@@ -14,7 +34,7 @@
#include "tn_post_code.h"
-#ifdef TECHNEXION_EARLY_SETUP
+#ifdef __PRE_RAM__
// TechNexion's Post Code Initially.
void technexion_post_code_init(void)
@@ -116,7 +136,7 @@
device_t dev=0;
// SMBus Module and ACPI Block (Device 20, Function 0)
-#ifdef TECHNEXION_EARLY_SETUP
+#ifdef __PRE_RAM__
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0);
#else
dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0);
===================================================================
@@ -31,6 +31,7 @@
driver mainboard.o
object tn_post_code.o
+object speaker.o
#dir /drivers/si/3114
===================================================================
@@ -1,11 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
-
#define LED_MESSAGE_START 0xFF
#define LED_MESSAGE_FINISH 0x99
#define LED_MESSAGE_RAM 0x01
-#ifdef TECHNEXION_EARLY_SETUP
+#ifdef __PRE_RAM__
// TechNexion's Post Code Initially.
void technexion_post_code_init(void);
===================================================================
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifdef __PRE_RAM__
+
+#include <arch/cpu.h>
+#include "southbridge/amd/sb600/sb600.h"
+
+#else
+
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <../southbridge/amd/sb600/sb600.h>
+#include <delay.h>
+
+#endif // __PRE_RAM__
+
+#include "speaker.h"
+
+void speaker_init(uint8_t time) {
+ /* SB600 RRG.
+ * Options_0 - RW - 8 bits - [PM_Reg: 60h].
+ * SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output.
+ */
+#ifndef __PRE_RAM__
+ pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5)));
+#else
+ pmio_write(0x60, (pmio_read(0x60) | (1<<5)));
+#endif // __PRE_RAM__
+
+ /* SB600 RRG.
+ * Tmr1CntrlWord - RW - 8 bits - [IO_Reg: 43h].
+ * ModeSelect, bit[3:1]=011b, Square wave output.
+ * CmmandSelect, bit[5:4]=11b, Read/write least, and then most significant byte.
+ * CounterSelect, bit[7:6]=10b, Select counter 2.
+ */
+ outb(0xb6, 0x43);
+
+
+ /* SB600 RRG.
+ * TimerCh2- RW - 8 bits - [IO_Reg: 42h].
+ */
+ outb(time, 0x42);
+}
+
+void speaker_on_nodelay(void) {
+ /* SB600 RRG.
+ * Nmi_Status - RW - 8 bits - [IO_Reg: 61h].
+ * SpkrEnable, bit[0]=1b, Enable counter 2
+ * SpkrTmrEnable, bit[1]=1b, Speaker timer on
+ */
+ outb(inb(0x61) | 0x03, 0x61);
+}
+
+void speaker_on_delay(void) {
+ /* SB600 RRG.
+ * Nmi_Status - RW - 8 bits - [IO_Reg: 61h].
+ * SpkrEnable, bit[0]=1b, Enable counter 2
+ * SpkrTmrEnable, bit[1]=1b, Speaker timer on
+ */
+ outb(inb(0x61) | 0x03, 0x61);
+ mdelay(100);
+}
+
+void speaker_off_nodelay(void) {
+ /* SB600 RRG.
+ * Nmi_Status - RW - 8 bits - [IO_Reg: 61h].
+ * SpkrEnable, bit[0]=0b, Disable counter 2
+ * SpkrTmrEnable, bit[1]=0b, Speaker timer off
+ */
+ outb(inb(0x61) & ~0x03, 0x61);
+}
+
+void speaker_off_delay(void) {
+ /* SB600 RRG.
+ * Nmi_Status - RW - 8 bits - [IO_Reg: 61h].
+ * SpkrEnable, bit[0]=0b, Disable counter 2
+ * SpkrTmrEnable, bit[1]=0b, Speaker timer off
+ */
+ outb(inb(0x61) & ~0x03, 0x61);
+ mdelay(100);
+}
+
===================================================================
@@ -28,6 +28,7 @@
#include <../southbridge/amd/sb600/sb600.h>
#include "chip.h"
#include "tn_post_code.h"
+//#include "speaker.h" // test buzzer
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
@@ -184,6 +185,12 @@
uma_memory_base, uma_memory_size);
#endif
technexion_post_code(LED_MESSAGE_FINISH);
+ // test buzzer
+ //speaker_on_delay();
+ //speaker_off_delay();
+ //speaker_on_delay();
+ //speaker_off_nodelay();
+
}
struct chip_operations mainboard_ops = {
Hi, I had fixing non-ascii characters in the comments. Thanks. Signed-off: Libra Li <libra.li@technexion.com> 2009/11/25 Bao, Zheng <Zheng.Bao@amd.com> > I haven't apply your patch, but in your patch, > line 140, 150, 159, 166, 175, 185, 194, > have those chars. > > You can use the perl script to detect the non-ascii chars. I sense there > should be another better way. > > #!/usr/bin/perl > > my($content, $len); > > open(FILE, "< tim5690_buzzer_2.patch") || die "Unable to open file small. > <$!>\n"; > > while( chomp($content = <FILE>) ) { > $len = length($content); > for( $i = 0; $i < $len; $i++ ) { > if( ord(substr($content, $i, 1)) > 127 ) > { > print "$content\n"; > last; > } > } > } > close(FILE); > > exit 0 > ~ > > > > > -----Original Message----- > From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] > On Behalf Of Bao, Zheng > Sent: Wednesday, November 25, 2009 11:32 AM > To: Libra Li > Cc: coreboot > Subject: Re: [coreboot] [PATCH] The buzzer of TechNexion TIM-5690. > > There is some non-ascii characters in the comments. Please fix it. > After that, > > Acked-by: Zheng Bao <zheng.bao@amd.com> > > Zheng > ________________________________________ > From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] > On Behalf Of Libra Li > Sent: Wednesday, November 25, 2009 9:46 AM > To: Myles Watson > Cc: coreboot > Subject: Re: [coreboot] [PATCH] The buzzer of TechNexion TIM-5690. > > Hi, Myles, Coreboot, > > I had change EARLY_STAGE into __PRE_RAM__. It's okay. > Thanks. > > Signed-off: Libra Li <libra.li@technexion.com> > > 2009/11/25 Myles Watson <mylesgw@gmail.com> > 2009/11/24 Libra Li <librali1977@gmail.com>: > > Hi, > > > > This patch is buzzer function of TechNexion TIM-5690. > > That isn't everyone needs. So I don't put in public areas. > > Thanks. > > > > Signed-off: Libra Li <libra.li@technexion.com> > Could you use __PRE_RAM__ instead of EARLY_STAGE? Does it mean > something different? > > Thanks, > Myles > > > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > >