Patchwork : Add superio SMSC sch4304 support.

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Submitter Bao, Zheng
Date 2009-11-26 02:11:43
Message ID <DD1CC71B621B004FA76856E5129D6B17033C155E@sbjgexmb1.amd.com>
Download mbox | patch
Permalink /patch/599/
State Accepted
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Comments

Bao, Zheng - 2009-11-26 02:11:43
Does anyone review it before it is drowned? 

Zheng


-----Original Message-----
From: coreboot-bounces+zheng.bao=amd.com@coreboot.org
[mailto:coreboot-bounces+zheng.bao=amd.com@coreboot.org] On Behalf Of
Bao, Zheng
Sent: Tuesday, November 24, 2009 11:23 AM
To: coreboot
Subject: [coreboot] [PATCH]: Add superio sch4304 support.

Add support of superio sch4304. The Device id is 0x90. The number of
X-BUS
logical device is 11.

I have not get the board to test it. I will have one. But I believe it
is
right, isn't it?

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Uwe Hermann - 2009-11-26 08:15:44
Hi,

On Thu, Nov 26, 2009 at 10:11:43AM +0800, Bao, Zheng wrote:
> Does anyone review it before it is drowned? 

I can't find the datasheet right now, but if the ID is 0x90 and
the numbers you added in that table are the Super I/O LDNs, then
this is

Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

The Super I/O only has FDC PP SP1 SP2 KBC XBUS RT as LDNs, correct?


>       // Chip   FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB
[...]
>  	{SCH3112,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
>  	{SCH5307,  {0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10, -1, -1}},
>  	{SCH5027D, {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, 11}},
> +	{SCH4304,  {0, 3, 4,  5, -1,  7, -1,  11, -1,  -1, -1, -1, 10, -1, -1}},


Uwe.
Bao, Zheng - 2009-11-26 08:47:33
The datasheet is not public now, isn't it?
Does coreboot has the NDA or something else to release sch4304?

Zheng


-----Original Message-----
From: Uwe Hermann [mailto:uwe@hermann-uwe.de] 
Sent: Thursday, November 26, 2009 4:16 PM
To: Bao, Zheng
Cc: coreboot
Subject: Re: [coreboot] [PATCH]: Add superio SMSC sch4304 support.

Hi,

On Thu, Nov 26, 2009 at 10:11:43AM +0800, Bao, Zheng wrote:
> Does anyone review it before it is drowned? 

I can't find the datasheet right now, but if the ID is 0x90 and
the numbers you added in that table are the Super I/O LDNs, then
this is

Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

The Super I/O only has FDC PP SP1 SP2 KBC XBUS RT as LDNs, correct?


>       // Chip   FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT
ACPI SMB
[...]
>  	{SCH3112,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10,
-1, -1}},
>  	{SCH5307,  {0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10,
-1, -1}},
>  	{SCH5027D, {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10,
-1, 11}},
> +	{SCH4304,  {0, 3, 4,  5, -1,  7, -1,  11, -1,  -1, -1, -1, 10,
-1, -1}},


Uwe.

Patch

Index: src/superio/smsc/smscsuperio/superio.c
===================================================================
--- src/superio/smsc/smscsuperio/superio.c	(revision 4952)
+++ src/superio/smsc/smscsuperio/superio.c	(working copy)
@@ -61,6 +61,7 @@ 
 #define SCH3112		0x7c
 #define SCH5307		0x81	/* Rebranded LPC47B397(?) */
 #define SCH5027D	0x89
+#define SCH4304		0x90	/* SCH4304 */
 
 /* Register defines */
 #define DEVICE_ID_REG	0x20	/* Device ID register */
@@ -137,6 +138,7 @@ 
 	{SCH3112,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10,
-1, -1}},
 	{SCH5307,  {0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10,
-1, -1}},
 	{SCH5027D, {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10,
-1, 11}},
+	{SCH4304,  {0, 3, 4,  5, -1,  7, -1,  11, -1,  -1, -1, -1, 10,
-1, -1}},
 };
 
 /**