From patchwork Wed Dec  2 15:34:38 2009
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Subject: Intel Poulsbo chipset support
Date: Wed, 02 Dec 2009 15:34:38 -0000
From: Adam Jurkowski <adam.jurkowski@kontron.pl>
X-Patchwork-Id: 621
Message-Id: <4B16890E.4000301@kontron.pl>
To: flashrom@flashrom.org

Add support for Intel Poulsbo chipset.

Signed-off-by: Adam Jurkowski <adam.jurkowski@kontron.pl>


Index: chipset_enable.c
===================================================================
--- chipset_enable.c	(revision 791)
+++ chipset_enable.c	(working copy)
@@ -4,6 +4,7 @@
  * Copyright (C) 2000 Silicon Integrated System Corporation
  * Copyright (C) 2005-2009 coresystems GmbH
  * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2009 Kontron Modular Computers GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -399,6 +400,43 @@
 	return enable_flash_ich(dev, name, 0xdc);
 }
 
+static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
+{
+	uint16_t old, new;
+
+	/*
+	 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
+	 * just treating it as 8 bit wide seems to work fine in practice.
+	 */
+	old = pci_read_word(dev, 0xd8);
+
+	printf_debug("BIOS Lock Enable: %sabled, ",
+		     (old & (1 << 1)) ? "en" : "dis");
+	printf_debug("BIOS Write Enable: %sabled, ",
+		     (old & (1 << 0)) ? "en" : "dis");
+	printf_debug("BIOS Prefetch Enable: %sabled, ",
+		     (old & (1 << 8)) ? "en" : "dis");
+	printf_debug("BIOS_CNTL is 0x%x\n", old);
+
+	new = old | 1;
+	new &= ~(0x100);
+
+	pci_write_word(dev, 0xd8, new);
+
+	if (pci_read_word(dev, 0xd8) != new) {
+		printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0xd8, new, name);
+	}
+	
+	old = pci_read_word(dev, 0xd6);
+	new = old |= 0xf000;
+	pci_write_word(dev, 0xd6, new);
+
+	new = 0x0000;
+	pci_write_word(dev, 0xd2, new);
+	return 0;
+}
+
+
 #define ICH_STRAP_RSVD 0x00
 #define ICH_STRAP_SPI  0x01
 #define ICH_STRAP_PCI  0x02
@@ -1139,6 +1177,7 @@
 	{0x8086, 0x7000, OK, "Intel", "PIIX3",		enable_flash_piix4},
 	{0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M",	enable_flash_piix4},
 	{0x8086, 0x122e, OK, "Intel", "PIIX",		enable_flash_piix4},
+	{0x8086, 0x8119, OK, "Intel", "Poulsbo",	enable_flash_poulsbo},
 	{0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4",  enable_flash_nvidia_nforce2},
 	{0x10de, 0x0050, OK, "NVIDIA", "CK804",		enable_flash_ck804}, /* LPC */
 	{0x10de, 0x0051, OK, "NVIDIA", "CK804",		enable_flash_ck804}, /* Pro */