Patchwork cannot work on Intel ICH7/ICH7R & SST SST25VF016B (2048 KB, SPI)

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Submitter Water Chen
Date 2009-12-11 07:23:46
Message ID <13e5c51d0912102323sa2d76aek3566fffde1db48e9@mail.gmail.com>
Download mbox | patch
Permalink /patch/638/
State Superseded
Headers show

Comments

Water Chen - 2009-12-11 07:23:46
Hi,

According to the Device Operation Instructions in page 8 in
SST25VF016B datasheet (http://www.sst.com/dotAsset/40371.pdf), I
modify OPCODES O_ST_M25P as below. Then flashrom can flash BIOS
successfully.
Can someone check if any problem or side effect to other boards?

Electronic Manufacturer Signature
 	 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1},	// Write Status Register

# ./flashrom -w 7sll2069.ROM
flashrom v0.9.1-r796
No coreboot table found.
Found chipset "Intel ICH7/ICH7R", enabling flash write... OK.
This chipset supports the following protocols: SPI.
Calibrating delay loop... OK.
Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000.
Flash image seems to be a legacy BIOS. Disabling checks.
Writing flash chip... Erasing flash before programming... Erasing
flash chip... SUCCESS.
done.
COMPLETE.
Verifying flash... VERIFIED.

Thank you.
Water Chen

2009/12/8 Water Chen <waterc@gmail.com>:
> Hi,
>
> flashrom cannot work on Intel ICH7/ICH7R / SST SST25VF016B (2048 KB, SPI).
> MB: Supermicro X7SLM-L /
> http://www.supermicro.com/products/motherboard/Core2Duo/945/X7SLM-L.cfm
>
> The outputs of 'flashrom -V', 'lspci -nnvvvxxx', 'superiotool -deV',
> 'dd if=/dev/mem of=sm_x7slm.system.rom bs=64k count=1 skip=15' are
> attached.
>
> # ./flashrom -w BIOS_X7SLM-L.ROM
> flashrom v0.9.1-r792
> No coreboot table found.
> Found chipset "Intel ICH7/ICH7R", enabling flash write... OK.
> This chipset supports the following protocols: SPI.
> Calibrating delay loop... OK.
> Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000.
> Flash image seems to be a legacy BIOS. Disabling checks.
> Writing flash chip... spi_write_status_register failed during command
> execution spi_write_status_register failed Erasing flash before
> programming... Erasing flash chip... spi_write_status_register failed
> during command execution spi_write_status_register failed
> spi_disable_blockprotect failed FAILED!
> ERASE FAILED!
> FAILED!
> Your flash chip is in an unknown state.
> Get help on IRC at irc.freenode.net (channel #flashrom) or mail
> flashrom@flashrom.org!
> -------------------------------------------------------------------------------
> DO NOT REBOOT OR POWEROFF!
>
> Thank you.
> Water Chen
>
Luc Verhaegen - 2009-12-11 08:54:11
On Fri, Dec 11, 2009 at 03:23:46PM +0800, Water Chen wrote:
> Hi,
> 
> According to the Device Operation Instructions in page 8 in
> SST25VF016B datasheet (http://www.sst.com/dotAsset/40371.pdf), I
> modify OPCODES O_ST_M25P as below. Then flashrom can flash BIOS
> successfully.
> Can someone check if any problem or side effect to other boards?
> 
> Index: flashrom/ichspi.c
> ===================================================================
> --- flashrom/ichspi.c	(revision 796)
> +++ flashrom/ichspi.c	(working copy)
> @@ -174,7 +174,7 @@
>  	{
>  	 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1},	// Write Byte
>  	 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0},	// Read Data
> -	 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1},	// Erase Sector
> +	 {JEDEC_EWSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0},	// Enable Write
> Status Register
>  	 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0},	// Read Device Status Reg
>  	 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0},	// Read
> Electronic Manufacturer Signature
>  	 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1},	// Write Status Register
> 
> # ./flashrom -w 7sll2069.ROM
> flashrom v0.9.1-r796
> No coreboot table found.
> Found chipset "Intel ICH7/ICH7R", enabling flash write... OK.
> This chipset supports the following protocols: SPI.
> Calibrating delay loop... OK.
> Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000.
> Flash image seems to be a legacy BIOS. Disabling checks.
> Writing flash chip... Erasing flash before programming... Erasing
> flash chip... SUCCESS.
> done.
> COMPLETE.
> Verifying flash... VERIFIED.
> 
> Thank you.
> Water Chen

Cool. Nice work. I think that Carldani might be able to tell offhand 
what effect this has on other chips.

Luc Verhaegen.

Patch

Index: flashrom/ichspi.c
===================================================================
--- flashrom/ichspi.c	(revision 796)
+++ flashrom/ichspi.c	(working copy)
@@ -174,7 +174,7 @@ 
 	{
 	 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1},	// Write Byte
 	 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0},	// Read Data
-	 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1},	// Erase Sector
+	 {JEDEC_EWSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0},	// Enable Write
Status Register
 	 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0},	// Read Device Status Reg
 	 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0},	// Read