Patchwork [MSRTOOL] Add Geode GX2 processor support.

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Submitter Nils
Date 2009-12-18 20:04:34
Message ID <200912182104.34200.njacobs8@hetnet.nl>
Download mbox | patch
Permalink /patch/672/
State Not Applicable
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Comments

Nils - 2009-12-18 20:04:34
Hello all,
The attached patch (for review) brings support for the AMD Geode GX2 
processors to Msrtool.
It seems to work as i tested it on my Wyse Winterm S50.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>

Msrtool -l -s output(+ File attached):

msrtool 4966M
Detected system linux: Linux with /dev/cpu/*/msr
Detected target geodegx2: AMD Geode(tm) GX2
Detected target cs5536: AMD Geode(tm) CS5536

Thanks,Nils
msrtool 4966M
Detected system linux: Linux with /dev/cpu/*/msr
Detected target geodegx2: AMD Geode(tm) GX2
Detected target cs5536: AMD Geode(tm) CS5536


# geodegx2 MSRs:
# MC_CF07_DATA
# 63:60 D1_SZ DIMM1 Size
#    56 D1_MB DIMM1 Module Banks
#    52 D1_CB DIMM1 Component Banks
# 50:48 D1_PSZ DIMM1 Page Size
# 47:44 D0_SZ DIMM0 Size
#    40 D0_MB DIMM0 Module Banks
#    36 D0_CB DIMM0 Component Banks
# 34:32 D0_PSZ DIMM0 Page Size
# 29:28 EMR_BA Mode Register Set Bank Address
#    26 EMR_QFC Extended Mode Register FET Control
#    25 EMR_DRV Extended Mode Register Drive Strength Control
#    24 EMR_DLL Extended Mode Register DLL
#  23:8 REF_INT Refresh Interval
#   7:6 REF_STAG Refresh Staggering
#     3 REF_TST Test Refresh
#     1 SOFT_RST Software Reset
#     0 PROG_DRAM Program Mode Register in SDRAM
0x20000018 0x1007711300003400

# MC_CF8F_DATA
# 63:56 STALE_REQ GLIU Max Stale Request Count
# 52:51 XOR_BIT_SEL XOR Bit Select
#    50 XOR_MB0 XOR MB0 Enable
#    49 XOR_BA1 XOR BA1 Enable
#    48 XOR_BA0 XOR BA0 Enable
#    39 AP_B2B Autoprecharge Back-to-Back Command
#    38 AP_EN Autoprecharge
#    33 HOI_LOI High / Low Order Interleave Select
#    31 THZ_DLY tHZ Delay
# 30:28 CAS_LAT Read CAS Latency
# 27:24 REF2ACT ACT to ACT/REF Period. tRC
# 23:20 ACT2PRE ACT to PRE Period. tRAS
# 18:16 PRE2ACT PRE to ACT Period. tRP
# 14:12 ACT2CMD Delay Time from ACT to Read/Write. tRCD
#  11:8 ACT2ACT ACT(0) to ACT(1) Period. tRRD
#   7:6 DPLWR Data-in to PRE Period. tDPLW
#   5:4 DPLRD Data-in to PRE Period. tDPLR
#   2:0 DAL Data-in to ACT (REF) Period. tDAL
0x20000019 0x18000008296332a3

# MC_CF1017_DATA
#     8 PM1_UP_DLY PMode1 Up Delay
#   2:0 WR2DAT Write Command to Data Latency
0x2000001a 0x0000000000000101

# MC_CFPERF_CNT1
# 63:32 CNT0 Counter 0
#  31:0 CNT1 Counter 1
0x2000001b 0x0000000000000000

# MC_PERFCNT2
#    35 STOP_CNT1 Stop Counter 1
#    34 RST_CNT1 Reset Counter 1
#    33 STOP_CNT0 Stop Counter 0
#    32 RST_CNT0 Reset Counter 0
# 31:24 CNT1_MASK Counter 1 Mask
# 23:16 CNT1_DATA Counter 1 Data
#  15:8 CNT0_MASK Counter 0 Mask
#   7:0 CNT0_DATA Counter 0 Data
0x2000001c 0x0000000000ff00ff

# MC_CFCLK_DBUG
#    34 B2B_EN Back-to-Back Command Enable
#    32 MTEST_EN MTEST Enable
#     9 MASK_CKE[1:0] CKE Mask
#     8 MASK_CKE0 CKE0 Mask
#     7 CNTL_MSK1 Control Mask 1
#     6 CNTL_MSK0 Control Mask 0
#     5 ADRS_MSK Address Mask
0x2000001d 0x0000000000000000

# GLCP_DELAY_CONTROLS
#    63 EN Delay Settings Enable
# 60:56 GIO Delay Geode Companion Device
# 55:51 PCI_IN Delay PCI Inputs
# 50:46 PCI_OUT Delay PCI Outputs
# 40:36 DOTCLK Delay Dot Clock
# 35:31 DRGB Delay Digital RGBs
# 30:26 SDCLK_IN Delay SDRAM Clock Input
# 25:21 SDCLK_OUT Delay SDRAM Clock Output
# 20:16 MEM_CTL Delay Memory Controls
#     6 MEM_ODDOUT Delay Odd Memory Data Output Bits
#   3:2 DQS_CLK_IN Delay DQS Before Clocking Input
#   1:0 DQS_CLK_OUT Delay DQS Before Clocking Output
0x4c00000f 0x830d415f8ea0ad6f

# GLCP_SYS_RSTPLL
# 44:41 MDIV GLIU1 Divisor
# 40:38 VDIV CPU Core Divisor
# 37:32 FBDIV Feedback Devisor
# 31:26 SWFLAGS Software Flags
#    25 LOCK PLL Lock
#    24 LOCKWAIT Lock Wait
# 23:16 HOLD_COUNT Hold Count, divided by 16
#    15 BYPASS PLL Bypass
#    14 PD Power Down
#    13 RESETPLL PLL Reset
#    10 DDRMODE DDR Mode
#     9 VA_SEMI_SYNC_MODE Synchronous CPU Core and GLIU1
#     8 PCI_SEMI_SYNC_MODE Synchronous CPU Core and GLIU1
#     7 DSTALL Debug Stall
#   6:4 BOOTSTRAP_STAT Bootstrap Status
#     3 DOTPOSTDIV3 DOTPLL Post-Divide by 3
#     2 DOTPREMULT2 DOTPLL Pre-Multiply by 2
#     1 DOTPREDIV2 DOTPLL Pre-Divide by 2
#     0 CHIP_RESET Chip Reset
0x4c000014 0x0000022606de0070
# cs5536 MSRs:
# DIVIL_LBAR_IRQ
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:5 BASE_ADDR Base Address in I/O Space
0x51400008 0x0000f00100001000

# DIVIL_LBAR_KEL
# 63:44 MEM_MASK Memory Address Mask Value
#    32 LBAR_EN LBAR Enable
# 31:12 BASE_ADDR Base Address in Memory Space
0x51400009 0xfffff001efc00000

# DIVIL_LBAR_SMB
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:8 BASE_ADDR Base Address in I/O Space
0x5140000b 0x0000f00100006000

# DIVIL_LBAR_GPIO
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:8 BASE_ADDR Base Address in I/O Space
0x5140000c 0x0000f00100006100

# DIVIL_LBAR_MFGPT
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:8 BASE_ADDR Base Address in I/O Space
0x5140000d 0x0000f00100006200

# DIVIL_LBAR_ACPI
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:8 BASE_ADDR Base Address in I/O Space
0x5140000e 0x0000f00100009c00

# DIVIL_LBAR_PMS
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:7 BASE_ADDR Base Address in I/O Space
0x5140000f 0x0000f00100009d00

# DIVIL_BALL_OPTS
# 11:10 SEC_BOOT_LOC Secondary Boot Location
#   9:8 BOOT_OP_LATCHED Latched Value of Boot Option
#     6 PIN_OPT_LALL All LPC Pin Option Selection
#     5 PIN_OPT_LIRQ LPC_SERIRQ or GPIO21 Pin Option Selection
#     4 PIN_OPT_LDRQ LPC_DRQ# or GPIO20 Pin Option Selection
#   3:2 PRI_BOOT_LOC Primary Boot Location
#     0 PIN_OPT_IDE IDE or Flash Controller Pin Function Selection
0x51400015 0x0000000000000071

# PIC_YSEL_LOW
# 31:28 MAP_Y7 Map Unrestricted Y Input 7
# 27:24 MAP_Y6 Map Unrestricted Y Input 6
# 23:20 MAP_Y5 Map Unrestricted Y Input 5
# 19:16 MAP_Y4 Map Unrestricted Y Input 4
# 15:12 MAP_Y3 Map Unrestricted Y Input 3
#  11:8 MAP_Y2 Map Unrestricted Y Input 2
#   7:4 MAP_Y1 Map Unrestricted Y Input 1
#   3:0 MAP_Y0 Map Unrestricted Y Input 0
0x51400020 0x00000000bb050a00

# PIC_YSEL_HIGH
# 31:28 MAP_Y15 Map Unrestricted Y Input 15
# 27:24 MAP_Y14 Map Unrestricted Y Input 14
# 23:20 MAP_Y13 Map Unrestricted Y Input 13
# 19:16 MAP_Y12 Map Unrestricted Y Input 12
# 15:12 MAP_Y11 Map Unrestricted Y Input 11
#  11:8 MAP_Y10 Map Unrestricted Y Input 10
#   7:4 MAP_Y9 Map Unrestricted Y Input 9
#   3:0 MAP_Y8 Map Unrestricted Y Input 8
0x51400021 0x0000000004000000

# PIC_ZSEL_LOW
# 31:28 MAP_Z7 Map Unrestricted Z Input 7
# 27:24 MAP_Z6 Map Unrestricted Z Input 6
# 23:20 MAP_Z5 Map Unrestricted Z Input 5
# 19:16 MAP_Z4 Map Unrestricted Z Input 4
# 15:12 MAP_Z3 Map Unrestricted Z Input 3
#  11:8 MAP_Z2 Map Unrestricted Z Input 2
#   7:4 MAP_Z1 Map Unrestricted Z Input 1
#   3:0 MAP_Z0 Map Unrestricted Z Input 0
0x51400022 0x0000000000002222

# PIC_ZSEL_HIGH
# 31:28 MAP_Z15 Map Unrestricted Z Input 15
# 27:24 MAP_Z14 Map Unrestricted Z Input 14
# 23:20 MAP_Z13 Map Unrestricted Z Input 13
# 19:16 MAP_Z12 Map Unrestricted Z Input 12
# 15:12 MAP_Z11 Map Unrestricted Z Input 11
#  11:8 MAP_Z10 Map Unrestricted Z Input 10
#   7:4 MAP_Z9 Map Unrestricted Z Input 9
#   3:0 MAP_Z8 Map Unrestricted Z Input 8
0x51400023 0x00000000000aa5b2

# PIC_IRQM_PRIM
#    15 PRIM15_MSK Primary Input 15 Mask
#    14 PRIM14_MSK Primary Input 14 Mask
#    13 PRIM13_MSK Primary Input 13 Mask
#    12 PRIM12_MSK Primary Input 12 Mask
#    11 PRIM11_MSK Primary Input 11 Mask
#    10 PRIM10_MSK Primary Input 10 Mask
#     9 PRIM9_MSK Primary Input 9 Mask
#     8 PRIM8_MSK Primary Input 8 Mask
#     7 PRIM7_MSK Primary Input 7 Mask
#     6 PRIM6_MSK Primary Input 6 Mask
#     5 PRIM5_MSK Primary Input 5 Mask
#     4 PRIM4_MSK Primary Input 4 Mask
#     3 PRIM3_MSK Primary Input 3 Mask
#     1 PRIM1_MSK Primary Input 1 Mask
#     0 PRIM0_MSK Primary Input 0 Mask
0x51400024 0x000000000000ffff

# PIC_IRQM_LPC
#    15 LPC15_EN LPC Input 15 Enable
#    14 LPC14_EN LPC Input 14 Enable
#    13 LPC13_EN LPC Input 13 Enable
#    12 LPC12_EN LPC Input 12 Enable
#    11 LPC11_EN LPC Input 11 Enable
#    10 LPC10_EN LPC Input 10 Enable
#     9 LPC9_EN LPC Input 9 Enable
#     8 LPC8_EN LPC Input 8 Enable
#     7 LPC7_EN LPC Input 7 Enable
#     6 LPC6_EN LPC Input 6 Enable
#     5 LPC5_EN LPC Input 5 Enable
#     4 LPC4_EN LPC Input 4 Enable
#     3 LPC3_EN LPC Input 3 Enable
#     1 LPC1_EN LPC Input 1 Enable
#     0 LPC0_EN LPC Input 0 Enable
0x51400025 0x0000000000000000

# PIC_XIRR_STS_LOW
#    31 IG7_STS_Z Unrestricted Source Z Input 7
#    30 IG7_STS_Y Unrestricted Source Y Input 7
#    29 IG7_STS_LPC LPC Input 7
#    28 IG7_STS_PRIM Primary Input 7
#    27 IG6_STS_Z Unrestricted Source Z Input 6
#    26 IG6_STS_Y Unrestricted Source Y Input 6
#    25 IG6_STS_LPC LPC Input 6
#    24 IG6_STS_PRIM Primary Input 6
#    23 IG5_STS_Z Unrestricted Source Z Input 5
#    22 IG5_STS_Y Unrestricted Source Y Input 5
#    21 IG5_STS_LPC LPC Input 5
#    20 IG5_STS_PRIM Primary Input 5
#    19 IG4_STS_Z Unrestricted Source Z Input 4
#    18 IG4_STS_Y Unrestricted Source Y Input 4
#    17 IG4_STS_LPC LPC Input 4
#    16 IG4_STS_PRIM Primary Input 4
#    15 IG3_STS_Z Unrestricted Source Z Input 3
#    14 IG3_STS_Y Unrestricted Source Y Input 3
#    13 IG3_STS_LPC LPC Input 3
#    12 IG3_STS_PRIM Primary Input 3
#    11 IG2_STS_Z Unrestricted Source Z Input 2
#    10 IG2_STS_Y Unrestricted Source Y Input 2
#     7 IG1_STS_Z Unrestricted Source Z Input 1
#     6 IG1_STS_Y Unrestricted Source Y Input 1
#     5 IG1_STS_LPC LPC Input 1
#     4 IG1_STS_PRIM Primary Input 1
#     1 IG0_STS_LPC LPC Input 0
#     0 IG0_STS_PRIM Primary Input 0
0x51400026 0x0000000000000001

# PIC_XIRR_STS_HIGH
#    31 IG15_STS_Z Unrestricted Source Z Input 15
#    30 IG15_STS_Y Unrestricted Source Y Input 15
#    29 IG15_STS_LPC LPC Input 15
#    28 IG15_STS_PRIM Primary Input 15
#    27 IG14_STS_Z Unrestricted Source Z Input 14
#    26 IG14_STS_Y Unrestricted Source Y Input 14
#    25 IG14_STS_LPC LPC Input 14
#    24 IG14_STS_PRIM Primary Input 14
#    23 IG13_STS_Z Unrestricted Source Z Input 13
#    22 IG13_STS_Y Unrestricted Source Y Input 13
#    21 IG13_STS_LPC LPC Input 13
#    20 IG13_STS_PRIM Primary Input 13
#    19 IG12_STS_Z Unrestricted Source Z Input 12
#    18 IG12_STS_Y Unrestricted Source Y Input 12
#    17 IG12_STS_LPC LPC Input 12
#    16 IG12_STS_PRIM Primary Input 12
#    15 IG11_STS_Z Unrestricted Source Z Input 11
#    14 IG11_STS_Y Unrestricted Source Y Input 11
#    13 IG11_STS_LPC LPC Input 11
#    12 IG11_STS_PRIM Primary Input 11
#    11 IG10_STS_Z Unrestricted Source Z Input 10
#    10 IG10_STS_Y Unrestricted Source Y Input 10
#     9 IG10_STS_LPC LPC Input 10
#     8 IG10_STS_PRIM Primary Input 10
#     7 IG9_STS_Z Unrestricted Source Z Input 9
#     6 IG9_STS_Y Unrestricted Source Y Input 9
#     5 IG9_STS_LPC LPC Input 9
#     4 IG9_STS_PRIM Primary Input 9
#     3 IG8_STS_Z Unrestricted Source Z Input 8
#     2 IG8_STS_Y Unrestricted Source Y Input 8
#     1 IG8_STS_LPC LPC Input 8
#     0 IG8_STS_PRIM Primary Input 8
0x51400027 0x0000000000000000
Joseph Smith - 2009-12-21 02:22:33
On 12/18/2009 03:04 PM, Nils wrote:
> Hello all,
> The attached patch (for review) brings support for the AMD Geode GX2
> processors to Msrtool.
> It seems to work as i tested it on my Wyse Winterm S50.
>
> Signed-off-by: Nils Jacobs<njacobs8@hetnet.nl>
>
> Msrtool -l -s output(+ File attached):
>
> msrtool 4966M
> Detected system linux: Linux with /dev/cpu/*/msr
> Detected target geodegx2: AMD Geode(tm) GX2
> Detected target cs5536: AMD Geode(tm) CS5536
>
Sweet! Great work :-)

Unfortunately I can't test this right now but is there anyone else that 
can test this so we can get it Acked?

Patch

Index: msrtool.c
===================================================================
--- msrtool.c	(revision 4978)
+++ msrtool.c	(working copy)
@@ -40,6 +40,7 @@ 
 struct pci_access *pacc = NULL;
 
 static struct targetdef alltargets[] = {
+	{ "geodegx2", "AMD Geode(tm) GX2", geodegx2_probe, geodegx2_msrs },
 	{ "geodelx", "AMD Geode(tm) LX", geodelx_probe, geodelx_msrs },
 	{ "cs5536", "AMD Geode(tm) CS5536", cs5536_probe, cs5536_msrs },
 	{ "K8", "AMD K8 Family", k8_probe, k8_msrs },
Index: Makefile.in
===================================================================
--- Makefile.in	(revision 4978)
+++ Makefile.in	(working copy)
@@ -26,7 +26,7 @@ 
 CFLAGS  = @CFLAGS@
 LDFLAGS = @LDFLAGS@
 
-TARGETS = geodelx.o cs5536.o k8.o
+TARGETS = geodegx2.o geodelx.o cs5536.o k8.o
 SYSTEMS = linux.o darwin.o freebsd.o
 OBJS    = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS)
 
Index: msrtool.h
===================================================================
--- msrtool.h	(revision 4978)
+++ msrtool.h	(working copy)
@@ -198,6 +198,10 @@ 
 
 /** target externs **/
 
+/* geodegx2.c */
+extern int geodegx2_probe(const struct targetdef *t);
+extern const struct msrdef geodegx2_msrs[];
+
 /* geodelx.c */
 extern int geodelx_probe(const struct targetdef *t);
 extern const struct msrdef geodelx_msrs[];
Index: geodegx2.c
===================================================================
--- geodegx2.c	(revision 0)
+++ geodegx2.c	(revision 0)
@@ -0,0 +1,518 @@ 
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (c) 2008 Peter Stuge <peter@stuge.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "msrtool.h"
+
+int geodegx2_probe(const struct targetdef *target) {
+	struct cpuid_t *id = cpuid();
+	return 5 == id->family && 5 == id->model;
+}
+
+const struct msrdef geodegx2_msrs[] = {
+	{ 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", {
+		{ 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "8 MB" },
+			{ MSR1(2), "16 MB" },
+			{ MSR1(3), "32 MB" },
+			{ MSR1(4), "64 MB" },
+			{ MSR1(5), "128 MB" },
+			{ MSR1(6), "256 MB" },
+			{ MSR1(7), "512 MB" },
+			{ MSR1(8), "Reserved" },
+			{ MSR1(9), "Reserved" },
+			{ MSR1(10), "Reserved" },
+			{ MSR1(11), "Reserved" },
+			{ MSR1(12), "Reserved" },
+			{ MSR1(13), "Reserved" },
+			{ MSR1(14), "Reserved" },
+			{ MSR1(15), "Reserved" },
+			{ BITVAL_EOT }
+		}},
+		{ 59, 3, RESERVED },
+		{ 56, 1, "D1_MB", "DIMM1 Module Banks", PRESENT_BIN, {
+			{ MSR1(0), "1 Module bank" },
+			{ MSR1(1), "2 Module banks" },
+			{ BITVAL_EOT }
+		}},
+		{ 55, 3, RESERVED },
+		{ 52, 1, "D1_CB", "DIMM1 Component Banks", PRESENT_BIN, {
+			{ MSR1(0), "2 Component banks" },
+			{ MSR1(1), "4 Component banks" },
+			{ BITVAL_EOT }
+		}},
+		{ 51, 1, RESERVED },
+		{ 50, 3, "D1_PSZ", "DIMM1 Page Size", PRESENT_BIN, {
+			{ MSR1(0), "1 KB" },
+			{ MSR1(1), "2 KB" },
+			{ MSR1(2), "4 KB" },
+			{ MSR1(3), "8 KB" },
+			{ MSR1(4), "16 KB" },
+			{ MSR1(5), "Reserved" },
+			{ MSR1(6), "Reserved" },
+			{ MSR1(7), "DIMM1 Not Installed" },
+			{ BITVAL_EOT }
+		}},
+		{ 47, 4, "D0_SZ", "DIMM0 Size", PRESENT_BIN, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "8 MB" },
+			{ MSR1(2), "16 MB" },
+			{ MSR1(3), "32 MB" },
+			{ MSR1(4), "64 MB" },
+			{ MSR1(5), "128 MB" },
+			{ MSR1(6), "256 MB" },
+			{ MSR1(7), "512 MB" },
+			{ MSR1(8), "Reserved" },
+			{ MSR1(9), "Reserved" },
+			{ MSR1(10), "Reserved" },
+			{ MSR1(11), "Reserved" },
+			{ MSR1(12), "Reserved" },
+			{ MSR1(13), "Reserved" },
+			{ MSR1(14), "Reserved" },
+			{ MSR1(15), "Reserved" },
+			{ BITVAL_EOT }
+		}},
+		{ 43, 3, RESERVED },
+		{ 40, 1, "D0_MB", "DIMM0 Module Banks", PRESENT_BIN, {
+			{ MSR1(0), "1 Module bank" },
+			{ MSR1(1), "2 Module banks" },
+			{ BITVAL_EOT }
+		}},
+		{ 39, 3, RESERVED },
+		{ 36, 1, "D0_CB", "DIMM0 Component Banks", PRESENT_BIN, {
+			{ MSR1(0), "2 Component banks" },
+			{ MSR1(1), "4 Component banks" },
+			{ BITVAL_EOT }
+		}},
+		{ 35, 1, RESERVED },
+		{ 34, 3, "D0_PSZ", "DIMM0 Page Size", PRESENT_BIN, {
+			{ MSR1(0), "1 KB" },
+			{ MSR1(1), "2 KB" },
+			{ MSR1(2), "4 KB" },
+			{ MSR1(3), "8 KB" },
+			{ MSR1(4), "16 KB" },
+			{ MSR1(5), "Reserved" },
+			{ MSR1(6), "Reserved" },
+			{ MSR1(7), "DIMM0 Not Installed" },
+			{ BITVAL_EOT }
+		}},
+		{ 31, 2, RESERVED },
+		{ 29, 2, "EMR_BA", "Mode Register Set Bank Address", PRESENT_BIN, {
+			{ MSR1(0), "Program the DIMM Mode Register" },
+			{ MSR1(1), "Program the DIMM Extended Mode Register" },
+			{ MSR1(2), "Reserved" },
+			{ MSR1(3), "Reserved" },
+			{ BITVAL_EOT }
+		}},
+		{ 27, 1, RESERVED },
+		{ 26, 1, "EMR_QFC", "Extended Mode Register FET Control", PRESENT_BIN, {
+			{ MSR1(0), "Enable" },
+			{ MSR1(1), "Disable" },
+			{ BITVAL_EOT }
+		}},
+		{ 25, 1, "EMR_DRV", "Extended Mode Register Drive Strength Control", PRESENT_BIN, {
+			{ MSR1(0), "Normal" },
+			{ MSR1(1), "Reduced" },
+			{ BITVAL_EOT }
+		}},
+		{ 24, 1, "EMR_DLL", "Extended Mode Register DLL", PRESENT_BIN, {
+			{ MSR1(0), "Enable" },
+			{ MSR1(1), "Disable" },
+			{ BITVAL_EOT }
+		}},
+		{ 23, 16, "REF_INT", "Refresh Interval", PRESENT_DEC, NOBITS },
+		{ 7, 2, "REF_STAG", "Refresh Staggering", PRESENT_DEC, {
+			{ MSR1(0), "4 SDRAM Clks" },
+			{ MSR1(1), "1 SDRAM Clks" },
+			{ MSR1(2), "2 SDRAM Clks" },
+			{ MSR1(3), "3 SDRAM Clks" },
+			{ BITVAL_EOT }
+		}},
+		{ 5, 2, RESERVED },
+		{ 3, 1, "REF_TST", "Test Refresh", PRESENT_BIN, NOBITS },
+		{ 2, 1, RESERVED },
+		{ 1, 1, "SOFT_RST", "Software Reset", PRESENT_BIN, NOBITS },
+		{ 0, 1, "PROG_DRAM", "Program Mode Register in SDRAM", PRESENT_BIN, NOBITS },
+		{ BITS_EOT }
+	}},
+	{ 0x20000019, MSRTYPE_RDWR, MSR2(0x18000008, 0x287337a3), "MC_CF8F_DATA", "Timing and Mode Program", {
+		{ 63, 8, "STALE_REQ", "GLIU Max Stale Request Count", PRESENT_DEC, NOBITS },
+		{ 55, 3, RESERVED },
+		{ 52, 2, "XOR_BIT_SEL", "XOR Bit Select", PRESENT_BIN, {
+			{ MSR1(0), "ADDR[18]" },
+			{ MSR1(1), "ADDR[19]" },
+			{ MSR1(2), "ADDR[20]" },
+			{ MSR1(3), "ADDR[21]" },
+			{ BITVAL_EOT }
+		}},
+		{ 50, 1, "XOR_MB0", "XOR MB0 Enable", PRESENT_BIN, {
+			{ MSR1(0), "Disabled" },
+			{ MSR1(1), "Enabled" },
+			{ BITVAL_EOT }
+		}},
+		{ 49, 1, "XOR_BA1", "XOR BA1 Enable", PRESENT_BIN, {
+			{ MSR1(0), "Disabled" },
+			{ MSR1(1), "Enabled" },
+			{ BITVAL_EOT }
+		}},
+		{ 48, 1, "XOR_BA0", "XOR BA0 Enable", PRESENT_BIN, {
+			{ MSR1(0), "Disabled" },
+			{ MSR1(1), "Enabled" },
+			{ BITVAL_EOT }
+		}},
+		{ 47, 8, RESERVED },
+		{ 39, 1, "AP_B2B", "Autoprecharge Back-to-Back Command", PRESENT_BIN, {
+			{ MSR1(0), "Enable" },
+			{ MSR1(1), "Disable" },
+			{ BITVAL_EOT }
+		}},
+		{ 38, 1, "AP_EN", "Autoprecharge", PRESENT_BIN, {
+			{ MSR1(0), "Enable" },
+			{ MSR1(1), "Disable" },
+			{ BITVAL_EOT }
+		}},		
+		{ 37, 4, RESERVED },
+		{ 33, 1, "HOI_LOI", "High / Low Order Interleave Select", PRESENT_BIN, {
+			{ MSR1(0), "Low Order Interleave" },
+			{ MSR1(1), "High Order Interleave" },
+			{ BITVAL_EOT }
+		}},
+		{ 32, 1, RESERVED },
+		{ 31, 1, "THZ_DLY", "tHZ Delay", PRESENT_BIN, NOBITS },
+		{ 30, 3, "CAS_LAT", "Read CAS Latency", PRESENT_BIN, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "Reserved" },
+			{ MSR1(2), "2 Clks" },
+			{ MSR1(3), "Reserved" },
+			{ MSR1(4), "Reserved" },
+			{ MSR1(5), "1.5 Clks" },
+			{ MSR1(6), "2.5 Clks" },
+			{ MSR1(7), "Reserved" },
+			{ BITVAL_EOT }
+		}},
+		{ 27, 4, "REF2ACT", "ACT to ACT/REF Period. tRC", PRESENT_BIN, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "1 Clks" },
+			{ MSR1(2), "2 Clks" },
+			{ MSR1(3), "3 Clks" },
+			{ MSR1(4), "4 Clks" },
+			{ MSR1(5), "5 Clks" },
+			{ MSR1(6), "7 Clks" },
+			{ MSR1(7), "8 Clks" },
+			{ MSR1(8), "9 Clks" },
+			{ MSR1(9), "10 Clks" },
+			{ MSR1(10), "11 Clks" },
+			{ MSR1(11), "12 Clks" },
+			{ MSR1(12), "13 Clks" },
+			{ MSR1(13), "14 Clks" },
+			{ MSR1(14), "15 Clks" },
+			{ MSR1(15), "16 Clks" },
+			{ BITVAL_EOT }
+		}},
+		{ 23, 4, "ACT2PRE", "ACT to PRE Period. tRAS", PRESENT_BIN, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "1 Clks" },
+			{ MSR1(2), "2 Clks" },
+			{ MSR1(3), "3 Clks" },
+			{ MSR1(4), "4 Clks" },
+			{ MSR1(5), "5 Clks" },
+			{ MSR1(6), "7 Clks" },
+			{ MSR1(7), "8 Clks" },
+			{ MSR1(8), "9 Clks" },
+			{ MSR1(9), "10 Clks" },
+			{ MSR1(10), "11 Clks" },
+			{ MSR1(11), "12 Clks" },
+			{ MSR1(12), "13 Clks" },
+			{ MSR1(13), "14 Clks" },
+			{ MSR1(14), "15 Clks" },
+			{ MSR1(15), "16 Clks" },
+			{ BITVAL_EOT }
+		}},
+		{ 19, 1, RESERVED },
+		{ 18, 3, "PRE2ACT", "PRE to ACT Period. tRP", PRESENT_BIN, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "1 Clks" },
+			{ MSR1(2), "2 Clks" },
+			{ MSR1(3), "3 Clks" },
+			{ MSR1(4), "4 Clks" },
+			{ MSR1(5), "5 Clks" },
+			{ MSR1(6), "6 Clks" },
+			{ MSR1(7), "7 Clks" },
+			{ BITVAL_EOT }
+		}},
+		{ 15, 1, RESERVED },
+		{ 14, 3, "ACT2CMD", "Delay Time from ACT to Read/Write. tRCD", PRESENT_BIN, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "1 Clks" },
+			{ MSR1(2), "2 Clks" },
+			{ MSR1(3), "3 Clks" },
+			{ MSR1(4), "4 Clks" },
+			{ MSR1(5), "5 Clks" },
+			{ MSR1(6), "6 Clks" },
+			{ MSR1(7), "Reserved" },
+			{ BITVAL_EOT }
+		}},
+		{ 11, 4, "ACT2ACT", "ACT(0) to ACT(1) Period. tRRD", PRESENT_BIN, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "1 Clks" },
+			{ MSR1(2), "2 Clks" },
+			{ MSR1(3), "3 Clks" },
+			{ MSR1(4), "4 Clks" },
+			{ MSR1(5), "5 Clks" },
+			{ MSR1(6), "6 Clks" },
+			{ MSR1(7), "7 Clks" },
+			{ MSR1(8), "Reserved" },
+			{ MSR1(9), "Reserved" },
+			{ MSR1(10), "Reserved" },
+			{ MSR1(11), "Reserved" },
+			{ MSR1(12), "Reserved" },
+			{ MSR1(13), "Reserved" },
+			{ MSR1(14), "Reserved" },
+			{ MSR1(15), "Reserved" },
+			{ BITVAL_EOT }
+		}},
+		{ 7, 2, "DPLWR", "Data-in to PRE Period. tDPLW", PRESENT_DEC, {
+			{ MSR1(0), "Invalid value" },
+			{ MSR1(1), "1 Clks" },
+			{ MSR1(2), "2 Clks" },
+			{ MSR1(3), "3 Clks" },
+			{ BITVAL_EOT }
+		}},
+		{ 5, 2, "DPLRD", "Data-in to PRE Period. tDPLR", PRESENT_DEC, {
+			{ MSR1(0), "Invalid value" },
+			{ MSR1(1), "1 Clks" },
+			{ MSR1(2), "2 Clks" },
+			{ MSR1(3), "3 Clks" },
+			{ BITVAL_EOT }
+		}},
+		{ 3, 1, RESERVED },
+		{ 2, 3, "DAL", "Data-in to ACT (REF) Period. tDAL", PRESENT_BIN, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "1 clks" },
+			{ MSR1(2), "2 Clks" },
+			{ MSR1(3), "3 Clks" },
+			{ MSR1(4), "4 Clks" },
+			{ MSR1(5), "5 Clks" },
+			{ MSR1(6), "6 Clks" },
+			{ MSR1(7), "7 Clks" },
+			{ BITVAL_EOT }
+		}},
+		{ BITS_EOT }
+	}},
+	{ 0x2000001a, MSRTYPE_RDWR, MSR2(0, 0), "MC_CF1017_DATA", "Feature Enables", {
+		{ 63, 55, RESERVED },
+		{ 8, 1, "PM1_UP_DLY", "PMode1 Up Delay", PRESENT_DEC, {
+			{ MSR1(0), "No delay" },
+			{ MSR1(1), "Enable delay" },
+			{ BITVAL_EOT }
+		}},
+			{ 7, 5, RESERVED },
+		{ 2, 3, "WR2DAT", "Write Command to Data Latency", PRESENT_DEC, {
+			{ MSR1(0), "Reserved" },
+			{ MSR1(1), "Value when unbuffered DDR SDRAMs are used" },
+			{ MSR1(2), "Value when registered DDR SDRAMs are used" },
+			{ MSR1(3), "Reserved" },
+			{ BITVAL_EOT }
+		}},
+		{ BITS_EOT }
+	}},
+	{ 0x2000001b, MSRTYPE_RDONLY, MSR2(0, 0), "MC_CFPERF_CNT1", "Performance Counters", {
+		{ 63, 32, "CNT0", "Counter 0", PRESENT_DEC, NOBITS },
+		{ 31, 32, "CNT1", "Counter 1", PRESENT_DEC, NOBITS },
+		{ BITS_EOT }
+	}},
+	{ 0x2000001c, MSRTYPE_RDWR, MSR2(0, 0x00ff00ff), "MC_PERFCNT2", "Counter and CAS Control", {
+		{ 63, 28, RESERVED },
+		{ 35, 1, "STOP_CNT1", "Stop Counter 1", PRESENT_DEC, {
+			{ MSR1(0), "Counter 1 counts" },
+			{ MSR1(1), "Stop Counter" },
+			{ BITVAL_EOT }
+		}},
+			{ 34, 1, "RST_CNT1", "Reset Counter 1", PRESENT_DEC, {
+			{ MSR1(0), "Do nothing" },
+			{ MSR1(1), "Reset counter 1" },
+			{ BITVAL_EOT }
+		}},
+			{ 33, 1, "STOP_CNT0", "Stop Counter 0", PRESENT_DEC, {
+			{ MSR1(0), "Counter 0 counts" },
+			{ MSR1(1), "Stop counter 0" },
+			{ BITVAL_EOT }
+		}},
+			{ 32, 1, "RST_CNT0", "Reset Counter 0", PRESENT_DEC, {
+			{ MSR1(0), "Do nothing" },
+			{ MSR1(1), "Reset counter 0" },
+			{ BITVAL_EOT }
+		}},
+		{ 31, 8, "CNT1_MASK", "Counter 1 Mask", PRESENT_BIN, NOBITS },
+		{ 23, 8, "CNT1_DATA", "Counter 1 Data", PRESENT_BIN, NOBITS },
+		{ 15, 8, "CNT0_MASK", "Counter 0 Mask", PRESENT_BIN, NOBITS },
+		{ 7, 8, "CNT0_DATA", "Counter 0 Data", PRESENT_BIN, NOBITS },
+		{ BITS_EOT }
+	}},
+	{ 0x2000001d, MSRTYPE_RDWR, MSR2(0, 0x300), "MC_CFCLK_DBUG", "Clocking and Debug", {
+		{ 63, 29, RESERVED },
+		{ 34, 1, "B2B_EN", "Back-to-Back Command Enable", PRESENT_BIN, {
+			{ MSR1(0), "Allow back-to-back commands" },
+			{ MSR1(1), "Disable back-to-back commands" },
+			{ BITVAL_EOT }
+		}},
+		{ 33, 1, RESERVED },
+		{ 32, 1, "MTEST_EN", "MTEST Enable", PRESENT_BIN, {
+			{ MSR1(0), "Disable" },
+			{ MSR1(1), "Enable" },
+			{ BITVAL_EOT }
+		}},
+		{ 31, 22, RESERVED },
+		{ 9, 1, "MASK_CKE[1:0]", "CKE Mask", PRESENT_BIN, {
+			{ MSR1(0), "CKE1 output enable unmasked" },
+			{ MSR1(1), "CKE1 output enable masked" },
+			{ BITVAL_EOT }
+		}},
+		{ 8, 1, "MASK_CKE0", "CKE0 Mask", PRESENT_BIN, {
+			{ MSR1(0), "CKE0 output enable unmasked" },
+			{ MSR1(1), "CKE0 output enable masked" },
+			{ BITVAL_EOT }
+		}},
+		{ 7, 1, "CNTL_MSK1", "Control Mask 1", PRESENT_BIN, {
+			{ MSR1(0), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked" },
+			{ MSR1(1), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable masked" },
+			{ BITVAL_EOT }
+		}},
+		{ 6, 1, "CNTL_MSK0", "Control Mask 0", PRESENT_BIN, {
+			{ MSR1(0), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked" },
+			{ MSR1(1), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable masked" },
+			{ BITVAL_EOT }
+		}},
+		{ 5, 1, "ADRS_MSK", "Address Mask", PRESENT_BIN, {
+			{ MSR1(0), "MA and BA output enable unmasked" },
+			{ MSR1(1), "MA and BA output enable masked" },
+			{ BITVAL_EOT }
+		}},
+		{ 4, 5, RESERVED },
+		{ BITS_EOT }
+	}},
+	{ 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", {
+		{ 63, 1, "EN", "Delay Settings Enable", PRESENT_DEC, {
+			{ MSR1(0), "Use default values" },
+			{ MSR1(1), "Use value in bits [62:0]" },
+			{ BITVAL_EOT }
+		}},
+		{ 62, 2, RESERVED },
+		{ 60, 5, "GIO", "Delay Geode Companion Device", PRESENT_DEC, NOBITS },
+		{ 55, 5, "PCI_IN", "Delay PCI Inputs", PRESENT_DEC, NOBITS },
+		{ 50, 5, "PCI_OUT", "Delay PCI Outputs", PRESENT_DEC, NOBITS },
+		{ 45, 5, RESERVED},
+		{ 40, 5, "DOTCLK", "Delay Dot Clock", PRESENT_DEC, NOBITS },
+		{ 35, 5, "DRGB", "Delay Digital RGBs", PRESENT_DEC, NOBITS },
+		{ 30, 5, "SDCLK_IN", "Delay SDRAM Clock Input", PRESENT_DEC, NOBITS },
+		{ 25, 5, "SDCLK_OUT", "Delay SDRAM Clock Output", PRESENT_DEC, NOBITS },
+		{ 20, 5, "MEM_CTL", "Delay Memory Controls", PRESENT_DEC, NOBITS },
+		{ 15, 9, RESERVED},
+		{ 6, 1, "MEM_ODDOUT", "Delay Odd Memory Data Output Bits", PRESENT_DEC, {
+			{ MSR1(0), "No Delay" },
+			{ MSR1(1), "Delay" },
+			{ BITVAL_EOT }
+		}},
+		{ 5, 2, RESERVED },
+		{ 3, 2, "DQS_CLK_IN", "Delay DQS Before Clocking Input", PRESENT_DEC, NOBITS },
+		{ 1, 2, "DQS_CLK_OUT", "Delay DQS Before Clocking Output", PRESENT_DEC, NOBITS },
+		{ BITS_EOT }
+	}},
+	{ 0x4c000014, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_SYS_RSTPLL", "GLCP System Reset and PLL Control", {
+		{ 63, 19, RESERVED },
+		{ 44, 4, "MDIV", "GLIU1 Divisor", PRESENT_BIN, {
+			{ MSR1(0), "Divide by 2" },
+			{ MSR1(1), "Divide by 3" },
+			{ MSR1(2), "Divide by 4" },
+			{ MSR1(3), "Divide by 5" },
+			{ MSR1(4), "Divide by 6" },
+			{ MSR1(5), "Divide by 7" },
+			{ MSR1(6), "Divide by 8" },
+			{ MSR1(7), "Divide by 9" },
+			{ MSR1(8), "Divide by 10" },
+			{ MSR1(9), "Divide by 11" },
+			{ MSR1(10), "Divide by 12" },
+			{ MSR1(11), "Divide by 13" },
+			{ MSR1(12), "Divide by 14" },
+			{ MSR1(13), "Divide by 15" },
+			{ MSR1(14), "Divide by 16" },
+			{ MSR1(15), "Divide by 17" },
+			{ BITVAL_EOT }
+		}},
+		{ 40, 3, "VDIV", "CPU Core Divisor", PRESENT_BIN, {
+			{ MSR1(0), "Divide by 2" },
+			{ MSR1(1), "Divide by 3" },
+			{ MSR1(2), "Divide by 4" },
+			{ MSR1(3), "Divide by 5" },
+			{ MSR1(4), "Divide by 6" },
+			{ MSR1(5), "Divide by 7" },
+			{ MSR1(6), "Divide by 8" },
+			{ MSR1(7), "Divide by 9" },
+			{ BITVAL_EOT }
+		}},
+		{ 37, 6, "FBDIV", "Feedback Devisor", PRESENT_DEC, NOBITS },
+		{ 31, 6, "SWFLAGS", "Software Flags", PRESENT_BIN, NOBITS },
+		{ 25, 1, "LOCK", "PLL Lock", PRESENT_DEC, {
+			{ MSR1(1), "PLL locked" },
+			{ MSR1(0), "PLL is not locked" },
+			{ BITVAL_EOT }
+		}},
+		{ 24, 1, "LOCKWAIT", "Lock Wait", PRESENT_DEC, {
+			{ MSR1(0), "Disable" },
+			{ MSR1(1), "Enable" },
+			{ BITVAL_EOT }
+		}},
+		{ 23, 8, "HOLD_COUNT", "Hold Count, divided by 16", PRESENT_DEC, NOBITS },
+		{ 15, 1, "BYPASS", "PLL Bypass", PRESENT_DEC, {
+			{ MSR1(0), "Use PLL as Clocksource" },
+			{ MSR1(1), "Use DOTREF as Clocksource" },
+			{ BITVAL_EOT }
+		}},
+		{ 14, 1, "PD", "Power Down", PRESENT_DEC, {
+			{ MSR1(0), "PLL active" },
+			{ MSR1(1), "PLL in power down mode" },
+			{ BITVAL_EOT }
+		}},
+			{ 13, 1, "RESETPLL", "PLL Reset", PRESENT_DEC, NOBITS },
+		{ 12, 2, RESERVED },
+		{ 10, 1, "DDRMODE", "DDR Mode", PRESENT_DEC, {
+			{ MSR1(0), "DDR communication enabled" },
+			{ MSR1(1), "Reserved" },
+			{ BITVAL_EOT }
+		}},
+		{ 9, 1, "VA_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
+			{ MSR1(1), "CPU does not use GLIU1 FIFO" },
+			{ MSR1(0), "The GLIU1 FIFO is used by the CPU" },
+			{ BITVAL_EOT }
+		}},
+		{ 8, 1, "PCI_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
+			{ MSR1(1), "PCI does not use mb_func_clk and pci_func_clk falling edges" },
+			{ MSR1(0), "Falling edges on mb_func_clk and pci_func_clk are used by PCI" },
+			{ BITVAL_EOT }
+		}},
+		{ 7, 1, "DSTALL", "Debug Stall", PRESENT_DEC, NOBITS },
+		{ 6, 3, "BOOTSTRAP_STAT", "Bootstrap Status", PRESENT_BIN, NOBITS },
+		{ 3, 1, "DOTPOSTDIV3", "DOTPLL Post-Divide by 3", PRESENT_DEC, NOBITS },
+		{ 2, 1, "DOTPREMULT2", "DOTPLL Pre-Multiply by 2", PRESENT_DEC, NOBITS },
+		{ 1, 1, "DOTPREDIV2", "DOTPLL Pre-Divide by 2", PRESENT_DEC, NOBITS },
+		{ 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS },
+		{ BITS_EOT }
+	}},
+	{ MSR_EOT }
+};