Patchwork sb/via/k8t890: add vga textmode code for k8m890 chrome igp.

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Submitter Luc Verhaegen
Date 2009-07-23 12:20:53
Message ID <20090723122053.GB26767@skynet.be>
Download mbox | patch
Permalink /patch/69/
State Accepted
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Luc Verhaegen - 2009-07-23 12:20:53
Luc Verhaegen.
sb/via/k8t890: add vga textmode code for k8m890 chrome igp.

Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
and through the general vga infrastructure i committed a month or two ago.
Add videoram_size option for k8m890 and the Asus M2V-MX SE.

Now the Asus M2V-MX SE will magically come up with a working standard VGA
80x25 textmode.

Many thanks to the people who worked hard on the Asus M2V-MX SE, and all
of its components; this vga bringup was a breeze thanks to your hard work
for this excellently supported board. And separate thanks to Rudolf Marek
for spurring me on and for providing a register dump.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
---
 src/mainboard/asus/m2v-mx_se/Options.lb    |    7 +-
 src/mainboard/asus/m2v-mx_se/cmos.layout   |    8 ++
 src/southbridge/via/k8t890/Config.lb       |    1 +
 src/southbridge/via/k8t890/k8m890_chrome.c |  179 ++++++++++++++++++++++++++++
 src/southbridge/via/k8t890/k8t890.h        |    3 +
 src/southbridge/via/k8t890/k8t890_dram.c   |   43 ++++++-
 6 files changed, 235 insertions(+), 6 deletions(-)
 create mode 100644 src/southbridge/via/k8t890/k8m890_chrome.c
Peter Stuge - 2009-07-23 13:18:49
Luc Verhaegen wrote:
> sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
> 
> Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
> and through the general vga infrastructure i committed a month or two ago.
> Add videoram_size option for k8m890 and the Asus M2V-MX SE.
> 
> Now the Asus M2V-MX SE will magically come up with a working standard VGA
> 80x25 textmode.
> 
> Many thanks to the people who worked hard on the Asus M2V-MX SE, and all
> of its components; this vga bringup was a breeze thanks to your hard work
> for this excellently supported board. And separate thanks to Rudolf Marek
> for spurring me on and for providing a register dump.
> 
> Signed-off-by: Luc Verhaegen <libv@skynet.be>

Acked-by: Peter Stuge <peter@stuge.se>
Rudolf Marek - 2009-07-23 15:29:01
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Hash: SHA1

Hi Luc,

looks fine. Please check the vga_init.c as we discussed on IRC. Also, maybe you
can develop simple patch that will write the memsize and speedgrade to scratch
registers.


Thanks,

Rudolf
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Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

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Luc Verhaegen - 2009-07-23 16:03:29
On Thu, Jul 23, 2009 at 05:29:01PM +0200, Rudolf Marek wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> Hi Luc,
> 
> looks fine. Please check the vga_init.c as we discussed on IRC.

For that, we need to figure out what these two registers really do 
depend on and what their effect is.

> Also, maybe you
> can develop simple patch that will write the memsize and speedgrade to scratch
> registers.

Tell you what; i'll go off for two days, and develop the solid PLL 
calculation routine needed to bring up the k8m890 in my unichrome 
driver.

Luc Verhaegen.
Luc Verhaegen - 2009-07-23 16:07:29
On Thu, Jul 23, 2009 at 03:18:49PM +0200, Peter Stuge wrote:
> Luc Verhaegen wrote:
> > sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
> > 
> > Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
> > and through the general vga infrastructure i committed a month or two ago.
> > Add videoram_size option for k8m890 and the Asus M2V-MX SE.
> > 
> > Now the Asus M2V-MX SE will magically come up with a working standard VGA
> > 80x25 textmode.
> > 
> > Many thanks to the people who worked hard on the Asus M2V-MX SE, and all
> > of its components; this vga bringup was a breeze thanks to your hard work
> > for this excellently supported board. And separate thanks to Rudolf Marek
> > for spurring me on and for providing a register dump.
> > 
> > Signed-off-by: Luc Verhaegen <libv@skynet.be>
> 
> Acked-by: Peter Stuge <peter@stuge.se>

Thanks: -> r4465

Luc Verhaegen.
Kevin O'Connor - 2009-07-26 18:21:34
On Thu, Jul 23, 2009 at 02:20:53PM +0200, Luc Verhaegen wrote:
> Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
> and through the general vga infrastructure i committed a month or two ago.
> Add videoram_size option for k8m890 and the Asus M2V-MX SE.
> 
> Now the Asus M2V-MX SE will magically come up with a working standard VGA
> 80x25 textmode.

Hi Luc,

With your code, will the SeaBIOS vgabios (make out/vgabios.bin) run on
the board?

-Kevin
Luc Verhaegen - 2009-07-27 14:06:45
On Sun, Jul 26, 2009 at 02:21:34PM -0400, Kevin O'Connor wrote:
> On Thu, Jul 23, 2009 at 02:20:53PM +0200, Luc Verhaegen wrote:
> > Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
> > and through the general vga infrastructure i committed a month or two ago.
> > Add videoram_size option for k8m890 and the Asus M2V-MX SE.
> > 
> > Now the Asus M2V-MX SE will magically come up with a working standard VGA
> > 80x25 textmode.
> 
> Hi Luc,
> 
> With your code, will the SeaBIOS vgabios (make out/vgabios.bin) run on
> the board?
> 
> -Kevin

No; a general VGA bios is a broken concept to begin with.

What you should know is that VGA is _not_ a standard, and one should 
never, ever try to change the mode without more detailed hw knowledge.
It is only a standard through the int10 and vbe interfaces, where the 
manufacturers vga bios does all the vga and hw specific stuff for you.

What such a general bios should do is find out, one way or another, what 
mode has been set and how to stuff things into the framebuffer.

In this case: mode 3h: 80x25 with 8x16 fonts, with the framebuffer 
living at 0xB8000 and with vga standard cursor and fb offset handling.

So a general int10 bios should find this out and then claim to only 
support this and absolutely nothing else.

Everything else requires a whole bunch of hw specific code, and while 
you could spend the rest of your days porting graphics drivers from fb 
or X to this code, i think there are much better ways to spend ones 
time.

Luc Verhaegen.
Luc Verhaegen - 2009-07-27 14:10:42
On Mon, Jul 27, 2009 at 04:06:45PM +0200, Luc Verhaegen wrote:
> 
> No; a general VGA bios is a broken concept to begin with.
> 
> What you should know is that VGA is _not_ a standard, and one should 
> never, ever try to change the mode without more detailed hw knowledge.
> It is only a standard through the int10 and vbe interfaces, where the 
> manufacturers vga bios does all the vga and hw specific stuff for you.
> 
> What such a general bios should do is find out, one way or another, what 
> mode has been set and how to stuff things into the framebuffer.
> 
> In this case: mode 3h: 80x25 with 8x16 fonts, with the framebuffer 
> living at 0xB8000 and with vga standard cursor and fb offset handling.
> 
> So a general int10 bios should find this out and then claim to only 
> support this and absolutely nothing else.
> 
> Everything else requires a whole bunch of hw specific code, and while 
> you could spend the rest of your days porting graphics drivers from fb 
> or X to this code, i think there are much better ways to spend ones 
> time.
> 
> Luc Verhaegen.

Let me further quantise this:

It would be great if there was int10 infrastructure which would do just 
the above.
* Seabios can show us its menu.
* Grub will then give us its menu too.
* The linux kernel will no longer think that it is talking to CGA and 
will use the correct fontsize while setting the cursor (so that we no 
longer get a floating cursor).

Luc Verhaegen.

Patch

diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb
index 75925ea..203f770 100644
--- a/src/mainboard/asus/m2v-mx_se/Options.lb
+++ b/src/mainboard/asus/m2v-mx_se/Options.lb
@@ -44,7 +44,7 @@  uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE
 uses CONFIG_STACK_SIZE
 uses CONFIG_HEAP_SIZE
-# uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_LB_MEM_TOPK
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_MAINBOARD_RESOURCES
@@ -74,6 +74,7 @@  uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
+uses CONFIG_VGA
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 # bx_b001- uses K8_HW_MEM_HOLE_SIZEK
@@ -101,7 +102,7 @@  default CONFIG_HAVE_HARD_RESET = 1
 default CONFIG_HAVE_PIRQ_TABLE = 0
 default CONFIG_IRQ_SLOT_COUNT = 11	# FIXME?
 default CONFIG_HAVE_MP_TABLE = 0
-default CONFIG_HAVE_OPTION_TABLE = 0	# FIXME
+default CONFIG_HAVE_OPTION_TABLE = 1	# FIXME
 # Move the default coreboot CMOS range off of AMD RTC registers.
 default CONFIG_LB_CKS_RANGE_START = 49
 default CONFIG_LB_CKS_RANGE_END = 122
@@ -136,6 +137,7 @@  default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
 # Only offset for SB chain?, default is yes(1).
 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
 
+default CONFIG_VGA = 1
 default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
 default CONFIG_PCI_ROM_RUN = 0		# Needed for VGA.
 default CONFIG_USE_DCACHE_RAM = 1
@@ -157,6 +159,7 @@  default CONFIG_HEAP_SIZE = 256 * 1024
 default CONFIG_LB_MEM_TOPK = 32768
 # to 1MB
 default CONFIG_RAMBASE = 0x1F00000
+default CONFIG_USE_OPTION_TABLE = 0
 # default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 default CONFIG_ROM_PAYLOAD = 1
 default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
diff --git a/src/mainboard/asus/m2v-mx_se/cmos.layout b/src/mainboard/asus/m2v-mx_se/cmos.layout
index 758c8dc..8276376 100644
--- a/src/mainboard/asus/m2v-mx_se/cmos.layout
+++ b/src/mainboard/asus/m2v-mx_se/cmos.layout
@@ -43,6 +43,7 @@  entries
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu
+448          3       e       10       videoram_size
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
@@ -90,6 +91,13 @@  enumerations
 9     5     37.5%
 9     6     25.0%
 9     7     12.5%
+# videoram_size: mimics the bits in the ramcontroller.
+10     1     8MB
+10     2     16MB
+10     3     32MB
+10     4     64MB
+10     5     128MB
+10     6     256MB
 
 checksums
 
diff --git a/src/southbridge/via/k8t890/Config.lb b/src/southbridge/via/k8t890/Config.lb
index 27e80b9..72502c2 100644
--- a/src/southbridge/via/k8t890/Config.lb
+++ b/src/southbridge/via/k8t890/Config.lb
@@ -25,3 +25,4 @@  driver k8t890_host_ctrl.o
 driver k8t890_pcie.o
 driver k8t890_traf_ctrl.o
 driver k8t890_error.o
+driver k8m890_chrome.o
diff --git a/src/southbridge/via/k8t890/k8m890_chrome.c b/src/southbridge/via/k8t890/k8m890_chrome.c
new file mode 100644
index 0000000..544b08e
--- /dev/null
+++ b/src/southbridge/via/k8t890/k8m890_chrome.c
@@ -0,0 +1,179 @@ 
+/*
+ * Copyright (C)  2007-2009  Luc Verhaegen <libv@skynet.be>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 51
+ * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h> /* for memset */
+#include "k8t890.h"
+
+#if CONFIG_VGA == 1
+#include <pc80/vga_io.h>
+#include <pc80/vga.h>
+#include <arch/io.h>
+
+/*
+ *
+ */
+static void
+chrome_vga_init(struct device *dev)
+{
+	vga_sr_write(0x10, 0x01); /* unlock extended regs */
+
+	vga_sr_mask(0x1A, 0x02, 0x02); /* enable mmio */
+
+	vga_sr_mask(0x1A, 0x40, 0x40); /* Software Reset */
+
+	vga_cr_mask(0x6A, 0x00, 0xC8); /* Disable CRTC2 & Simultaneous */
+
+	/* Make sure that non of the primary VGA overflow registers are set */
+	vga_cr_write(0x33, 0x00);
+	vga_cr_write(0x35, 0x00);
+	vga_cr_mask(0x11, 0x00, 0x30);
+
+	vga_sr_mask(0x16, 0x00, 0x40); /* Wire CRT to CRTC1 */
+	vga_cr_mask(0x36, 0x00, 0x30); /* Power on CRT */
+
+	/* Disable Extended Display Mode */
+	vga_sr_mask(0x15, 0x00, 0x02);
+
+	/* Disable Wrap-around */
+	vga_sr_mask(0x15, 0x00, 0x20);
+
+	/* Disable Extended Mode memory access */
+	vga_sr_mask(0x1A, 0x00, 0x08);
+
+	/* Make sure that we only touch CRTC1s DAC */
+	vga_sr_mask(0x1A, 0x00, 0x01);
+
+	/* Set up power to the clocks/crtcs */
+	vga_sr_mask(0x19, 0x7F, 0x7F); /* enable clock gating for all. */
+	vga_sr_mask(0x1B, 0xC0, 0xC0); /* secondary clock according to pm */
+	vga_sr_mask(0x1B, 0x20, 0x30); /* primary clock is always on */
+
+	/* set everything according to PM/Engine idle state except pci dma */
+	vga_sr_write(0x2D, 0xFF); /* Power management control 1 */
+	vga_sr_write(0x2E, 0xFB); /* Power management control 2 */
+	vga_sr_write(0x3F, 0xFF); /* Power management control 3 */
+
+	/* now set up the engine clock. */
+	vga_sr_write(0x47, 0xB8);
+	vga_sr_write(0x48, 0x08);
+	vga_sr_write(0x49, 0x03);
+
+	/* trigger engine clock setting */
+	vga_sr_mask(0x40, 0x01, 0x01);
+	vga_sr_mask(0x40, 0, 0x01);
+
+	vga_cr_mask(0x30, 0x04, 0x04); /* Enable PowerNow in primary path */
+	vga_cr_mask(0x36, 0x01, 0x01); /* Enable PCI Power Management */
+
+	/* Power now indicators... */
+	vga_cr_write(0x41, 0xB9);
+	vga_cr_write(0x42, 0xB4);
+	/* could these be the CRTC2 power now indicators? */
+	vga_cr_write(0x9D, 0x80); /* Power Now Ending position enable */
+	vga_cr_write(0x9E, 0xB4); /* Power Now Control 3 */
+
+	/* primary fifo setting */
+	vga_sr_mask(0x16, 0x28, 0xBF); /* pthreshold: 160 */
+	vga_sr_write(0x17, 0x60); /* max depth: 194 */
+	vga_sr_mask(0x18, 0x0E, 0xBF); /* high priority threshold: 56 */
+	vga_sr_write(0x1C, 0x54); /* Fetch count */
+
+	vga_sr_write(0x20, 0x40); /* display queue typical arbiter control 0 */
+	vga_sr_write(0x21, 0x40); /* display queue typical arbiter control 1 */
+	vga_sr_mask(0x22, 0x14, 0x1F); /* display queue expire number */
+
+	/* Typical Arbiter Control */
+	vga_sr_mask(0x41, 0x40, 0xF0); /* Request threshold */
+	vga_sr_mask(0x42, 0x20, 0x20); /* Support Fetch Cycle with Length 2 */
+
+	vga_sr_write(0x50, 0x1F); /* AGP Control Register */
+	vga_sr_write(0x51, 0xF5); /* AGP FIFO Control 1 */
+
+	vga_cr_mask(0x33, 0x08, 0x08); /* Enable Prefetch Mode */
+}
+
+#endif /* CONFIG_VGA */
+
+/*
+ *
+ */
+static void
+chrome_init(struct device *dev)
+{
+	uint32_t fb_size, fb_address;
+
+	fb_size = k8m890_host_fb_size_get();
+	if (!fb_size) {
+		printk_warning("Chrome: Device has not been initialised in the"
+			       " ramcontroller!\n");
+		return;
+	}
+
+	fb_address = pci_read_config32(dev, 0x10);
+	fb_address &= ~0x0F;
+	if (!fb_address) {
+		printk_warning("Chrome: No FB BAR assigned!\n");
+		return;
+	}
+
+	printk_info("Chrome: Using %dMB Framebuffer at 0x%08X.\n",
+		    fb_size, fb_address);
+
+	//k8m890_host_fb_direct_set(fb_address);
+
+#if CONFIG_VGA == 1
+	/* Now set up the VGA console */
+	vga_io_init(); /* Enable full IO access */
+
+	chrome_vga_init(dev);
+
+	vga_textmode_init();
+
+#if CONFIG_CONSOLE_VGA == 1
+	vga_console_init();
+#endif
+
+	printk_info("Chrome VGA Textmode initialized.\n");
+
+#if CONFIG_CONSOLE_VGA == 0
+	/* if we don't have console, at least print something... */
+	vga_line_write(0, "Chrome VGA Textmode initialized.");
+#endif
+
+#endif /* CONFIG_VGA */
+}
+
+static struct device_operations
+chrome_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = chrome_init,
+	.scan_bus         = 0,
+	.enable           = 0,
+};
+
+static const struct pci_driver unichrome_driver __pci_driver = {
+	.ops    = &chrome_ops,
+	.vendor = 0x1106,
+	.device = 0x3230,
+};
diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h
index 59d47ee..221aec7 100644
--- a/src/southbridge/via/k8t890/k8t890.h
+++ b/src/southbridge/via/k8t890/k8t890.h
@@ -43,4 +43,7 @@ 
 extern void writeback(struct device *dev, u16 where, u8 what);
 extern void dump_south(device_t dev);
 
+int k8m890_host_fb_size_get(void);
+//void k8m890_host_fb_direct_set(uint32_t fb_address);
+
 #endif
diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/k8t890_dram.c
index b32e5f8..3a5d97a 100644
--- a/src/southbridge/via/k8t890/k8t890_dram.c
+++ b/src/southbridge/via/k8t890/k8t890_dram.c
@@ -23,6 +23,7 @@ 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
+#include <pc80/mc146818rtc.h>
 #include <bitops.h>
 #include "k8t890.h"
 
@@ -104,18 +105,52 @@  extern uint64_t high_tables_base, high_tables_size;
 #endif
 }
 
+/*
+ *
+ */
+int
+k8m890_host_fb_size_get(void)
+{
+	struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
+					     PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
+	unsigned char tmp;
+
+	tmp = pci_read_config8(dev, 0xA1);
+	tmp >>= 4;
+	if (tmp & 0x08)
+		return 4 << (tmp & 7);
+	else
+		return 0;
+}
 
 static void dram_init_fb(struct device *dev)
 {
 	/* Important bits:
 	 * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg:
-	 * bits 6:4 X fbuffer size will be  2^(X+2) or 100 = 64MB, 101 = 128MB 
+	 * bits 6:4 X fbuffer size will be  2^(X+2) or 100 = 64MB, 101 = 128MB
 	 * bits 3:0 BASE [31:28]
 	 * reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access
 	 */
 	u8 tmp;
 	uint64_t proposed_base;
-	unsigned int fbsize = (K8M890_FBSIZEMB * 1024 * 1024);
+	unsigned int fbbits = 0;
+	unsigned int fbsize;
+	int ret;
+
+
+	ret = get_option(&fbbits, "videoram_size");
+	if (ret) {
+		printk_warning("Failed to get videoram size (error %d), using default.\n", ret);
+		fbbits = 5;
+ 	}
+
+	if ((fbbits < 1) || (fbbits > 7)) {
+		printk_warning("Invalid videoram size (%d), using default.\n",
+			       4 << fbbits);
+		fbbits = 5;
+	}
+
+	fbsize = 4 << (fbbits + 20);
 
 	resmax = NULL;
 	search_global_resources(
@@ -131,13 +166,13 @@  static void dram_init_fb(struct device *dev)
 	proposed_base = resmax->base + resmax->size - fbsize;
 	resmax->size -= fbsize;
 
-	printk_debug("VIA FB proposed base: %llx\n", proposed_base);
+	printk_info("K8M890: Using a %dMB framebuffer.\n", 4 << fbbits);
 
 	/* Step 1: enable UMA but no FB */
 	pci_write_config8(dev, 0xa1, 0x80);
 
 	/* Step 2: enough is just the FB size, the CPU accessible address is not needed */
-	tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4) | 0x80;
+	tmp = (fbbits << 4) | 0x80;
 	pci_write_config8(dev, 0xa1, tmp);
 
 	/* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */