Patchwork Memtest86+ failing on coreboot system.

login
register
about
Submitter Patrick Georgi
Date 2010-01-26 09:58:36
Message ID <4B5EBCCC.5020905@georgi-clan.de>
Download mbox | patch
Permalink /patch/840/
State Not Applicable
Headers show

Comments

Patrick Georgi - 2010-01-26 09:58:36
Am 25.01.2010 17:13, schrieb Knut Kujat:
> - booting interrupts for about 4 minutes on "Stage: loading
> fallback/coreboot_ram @ 0x200000 (360448 bytes), entry @ 0x200000"
>   
For this issue, the following change might help:
         /* Set the default memory type and enable fixed and variable MTRRs
          */

If it does, please let us know, so we can add it to the tree.

Regards,
Patrick
Knut Kujat - 2010-01-26 10:33:36
Patrick Georgi escribió:
> Am 25.01.2010 17:13, schrieb Knut Kujat:
>   
>> - booting interrupts for about 4 minutes on "Stage: loading
>> fallback/coreboot_ram @ 0x200000 (360448 bytes), entry @ 0x200000"
>>   
>>     
> For this issue, the following change might help:
> --- src/cpu/amd/mtrr/amd_earlymtrr.c    (revision 5054)
> +++ src/cpu/amd/mtrr/amd_earlymtrr.c    (working copy)
> @@ -45,8 +45,13 @@
>          /* enable write through caching so we can do execute in place
>           * on the flash rom.
>           */
> -        set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE,
> MTRR_TYPE_WRBACK);
> +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
> +#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
> +#else
> +#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
>  #endif
> +        set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE,
> MTRR_TYPE_WRBACK);
> +#endif
>
>          /* Set the default memory type and enable fixed and variable MTRRs
>           */
>
> If it does, please let us know, so we can add it to the tree.
>
> Regards,
> Patrick
>
>   
Hello,

#if defined(CONFIG_XIP_ROM_SIZE)
         /* enable write through caching so we can do execute in place
          * on the flash rom.
          */
         #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
           #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
         #else
           #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
         #endif
         set_var_mtrr(1, REAL_XIP_ROM_BASE,
CONFIG_XIP_ROM_SIZE,MTRR_TYPE_WRBACK);

#endif

It still hangs at

"Stage: loading
fallback/coreboot_ram @ 0x200000 (360448 bytes), entry @ 0x200000"

for exactly 2min 28sec so I think it speed up a little :).

Thanks I really appreciate your help.

Knut Kujat.

Patch

--- src/cpu/amd/mtrr/amd_earlymtrr.c    (revision 5054)
+++ src/cpu/amd/mtrr/amd_earlymtrr.c    (working copy)
@@ -45,8 +45,13 @@ 
         /* enable write through caching so we can do execute in place
          * on the flash rom.
          */
-        set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE,
MTRR_TYPE_WRBACK);
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
+        set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE,
MTRR_TYPE_WRBACK);
+#endif