===================================================================
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
+ * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -45,7 +45,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
-#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
/**
* The onboard 64MB PC133 memory does not have a SPD EEPROM so the
@@ -73,18 +72,33 @@
#include "lib/generic_sdram.c"
/**
- * The AC'97 Audio Controller I/O space registers are read only by default
- * so we need to enable them by setting register 0x41 to 0x01.
+ * Setup mainboard specific registers pre raminit.
*/
-static void ac97_io_enable(void)
+static void mb_early_setup(void)
{
- device_t dev;
+ /* - Hub Interface to PCI Bridge Registers - */
+ /* 12-Clock Retry Enable */
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
+ /* Master Latency Timer Count */
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+ /* I/O Address Base */
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
- /* Set the ac97 audio device staticly. */
- dev = PCI_DEV(0x0, 0x1f, 0x5);
-
- /* Enable access to the IO space. */
- pci_write_config8(dev, 0x41, 0x01);
+ /* - LPC Interface Bridge Registers - */
+ /* Delayed Transaction Enable */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
+ /* Disable the TCO Timer system reboot feature */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
+ /* CPU Frequency Strap */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
+ /* ACPI base address and enable Resource Indicator */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
+ /* Enable the SMBUS */
+ enable_smbus();
+ /* ACPI base address and disable Resource Indicator */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
+ /* ACPI Enable */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
}
static void main(unsigned long bist)
@@ -102,19 +116,20 @@
hard_reset();
}
+ /* Set southbridge and superio gpios */
+ mb_gpio_init();
+
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
- enable_smbus();
-
- /* Prevent the TCO timer from rebooting us */
- i82801xx_halt_tco_timer();
-
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
+ /* Setup mainboard specific registers */
+ mb_early_setup();
+
+ /* SDRAM init */
sdram_set_registers(memctrl);
sdram_set_spd_registers(memctrl);
sdram_enable(0, memctrl);
@@ -122,6 +137,4 @@
/* Check RAM. */
/* ram_check(0, 640 * 1024); */
/* ram_check(64512 * 1024, 65536 * 1024); */
-
- ac97_io_enable();
-}
+}
\ No newline at end of file
===================================================================
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
+ * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -45,10 +45,9 @@
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
-#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
/**
- * The onboard 128MB PC133 memory does not have a SPD EEPROM so the
+ * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
* values have to be set manually, the SO-DIMM socket is located in
* socket0 (0x50), and the onboard memory is located in socket1 (0x51).
*/
@@ -73,18 +72,33 @@
#include "lib/generic_sdram.c"
/**
- * The AC'97 Audio Controller I/O space registers are read only by default
- * so we need to enable them by setting register 0x41 to 0x01.
+ * Setup mainboard specific registers pre raminit.
*/
-static void ac97_io_enable(void)
+static void mb_early_setup(void)
{
- device_t dev;
+ /* - Hub Interface to PCI Bridge Registers - */
+ /* 12-Clock Retry Enable */
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
+ /* Master Latency Timer Count */
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+ /* I/O Address Base */
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
- /* Set the ac97 audio device staticly. */
- dev = PCI_DEV(0x0, 0x1f, 0x5);
-
- /* Enable access to the IO space. */
- pci_write_config8(dev, 0x41, 0x01);
+ /* - LPC Interface Bridge Registers - */
+ /* Delayed Transaction Enable */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
+ /* Disable the TCO Timer system reboot feature */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
+ /* CPU Frequency Strap */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
+ /* ACPI base address and enable Resource Indicator */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
+ /* Enable the SMBUS */
+ enable_smbus();
+ /* ACPI base address and disable Resource Indicator */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
+ /* ACPI Enable */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
}
static void main(unsigned long bist)
@@ -102,26 +116,25 @@
hard_reset();
}
+ /* Set southbridge and superio gpios */
+ mb_gpio_init();
+
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
- enable_smbus();
-
- /* Prevent the TCO timer from rebooting us */
- i82801xx_halt_tco_timer();
-
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
+ /* Setup mainboard specific registers */
+ mb_early_setup();
+
+ /* SDRAM init */
sdram_set_registers(memctrl);
sdram_set_spd_registers(memctrl);
sdram_enable(0, memctrl);
/* Check RAM. */
/* ram_check(0, 640 * 1024); */
- /* ram_check(130048 * 1024, 131072 * 1024); */
-
- ac97_io_enable();
-}
+ /* ram_check(64512 * 1024, 65536 * 1024); */
+}
Hello, This is a rework patch for the RCA RM4100 and Thomson IP1000. A few of the changes include: 1. Setting up the PCI Host Bridge registers (not doing this was causing random unexpected exception errors) 2. Setting up some LPC registers 3. dropping the early lpc code to disable the TCO timer. This probably can also be dropped from the i82801xx code too. To my suprise the is an LPC register that disables this completely (0xd4). 4. move gpio code to run earlier. 5. all this needs to be done pre-raminit Build and Run tested. See patch. Signed-off-by: Joseph Smith <joe@settoplinux.org>