| Submitter | Bao, Zheng |
|---|---|
| Date | 2010-02-02 03:25:29 |
| Message ID | <DD1CC71B621B004FA76856E5129D6B17036DA956@sbjgexmb1.amd.com> |
| Download | mbox | patch |
| Permalink | /patch/864/ |
| State | Accepted |
| Headers | show |
Comments
On 2/2/10 4:25 AM, Bao, Zheng wrote: > Index: src/arch/i386/smp/ioapic.c > =================================================================== > --- src/arch/i386/smp/ioapic.c (revision 5073) > +++ src/arch/i386/smp/ioapic.c (working copy) > @@ -110,7 +110,7 @@ > #endif > > /* Enable Virtual Wire Mode */ > - low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | > ExtINT; > + low = DISABLED; > high = bsp_lapicid << (56 - 32); > > io_apic_write(ioapic_base, 0x10, low); > Hm.. This will break quite some other boards... Is there any particular reason why the dbm690t will not work in virtual wire mode? I think either the sb600 code should call clear_ioapic() instead of setup_ioapic() or (maybe better) the setup_ioapic() function should get an additional parameter virtual_wire Anyways, maybe we should try to unify clear_ioapic and setup_ioapic (also, the function should create a device node and append it to the bridge it is called from) Stefan
I tried other board. The K8+rs690+sb600 and k8+rs780+sb700 don't work on current version, while fam10+rs780+sb700 works. I doubt that it has something to do the spurious interrupt or timer interrupt. I don't know. Do you have any idea? Zheng -----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Stefan Reinauer Sent: Wednesday, February 03, 2010 9:41 AM To: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH]: Disable ExtINT in ioapic.c On 2/2/10 4:25 AM, Bao, Zheng wrote: > Index: src/arch/i386/smp/ioapic.c > =================================================================== > --- src/arch/i386/smp/ioapic.c (revision 5073) > +++ src/arch/i386/smp/ioapic.c (working copy) > @@ -110,7 +110,7 @@ > #endif > > /* Enable Virtual Wire Mode */ > - low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | > ExtINT; > + low = DISABLED; > high = bsp_lapicid << (56 - 32); > > io_apic_write(ioapic_base, 0x10, low); > Hm.. This will break quite some other boards... Is there any particular reason why the dbm690t will not work in virtual wire mode? I think either the sb600 code should call clear_ioapic() instead of setup_ioapic() or (maybe better) the setup_ioapic() function should get an additional parameter virtual_wire Anyways, maybe we should try to unify clear_ioapic and setup_ioapic (also, the function should create a device node and append it to the bridge it is called from) Stefan
On Sun, Feb 28, 2010 at 10:53 PM, Bao, Zheng <Zheng.Bao@amd.com> wrote: > I tried other board. The K8+rs690+sb600 and k8+rs780+sb700 don't work on > current version, while fam10+rs780+sb700 works. I doubt that it has > something to do the spurious interrupt or timer interrupt. I don't know. > Do you have any idea? > That comment makes me think that the k8 lapic isn't setup correctly. There is a lot more lapic setup in the fam10 code for fid/vid support. We will have to look K8 more closely. I am seeing something similar on Pistachio when seabios enables the timer interrupt. I haven't tracked it down any farther yet. Marc
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, On K8 + K8M890 it works well, please let me know what to test. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkuMTWAACgkQ3J9wPJqZRNWxcQCfbXyqy7pivnyqp2tvj8MoZWOP HyIAnjXUJX3+xk2Y/0e80BX0gJT5CldJ =O44k -----END PGP SIGNATURE-----
Call the setup_ioapic in southbridge and see if linux hangs.
Zheng
-----Original Message-----
From: coreboot-bounces@coreboot.org
[mailto:coreboot-bounces@coreboot.org] On Behalf Of Rudolf Marek
Sent: Tuesday, March 02, 2010 7:27 AM
To: Marc Jones
Cc: Stefan Reinauer; Bao, Zheng; coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH]: Disable ExtINT in ioapic.c
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi,
On K8 + K8M890 it works well, please let me know what to test.
Rudolf
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Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
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HyIAnjXUJX3+xk2Y/0e80BX0gJT5CldJ
=O44k
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> Call the setup_ioapic in southbridge and see if linux hangs. > > Zheng Yes this is done, works fine. Check vt8237r_lpc.c Rudolf
On Tue, Feb 2, 2010 at 6:40 PM, Stefan Reinauer <stepan@coresystems.de> wrote: > On 2/2/10 4:25 AM, Bao, Zheng wrote: >> Index: src/arch/i386/smp/ioapic.c >> =================================================================== >> --- src/arch/i386/smp/ioapic.c (revision 5073) >> +++ src/arch/i386/smp/ioapic.c (working copy) >> @@ -110,7 +110,7 @@ >> #endif >> >> /* Enable Virtual Wire Mode */ >> - low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | >> ExtINT; >> + low = DISABLED; >> high = bsp_lapicid << (56 - 32); >> >> io_apic_write(ioapic_base, 0x10, low); >> > > Hm.. This will break quite some other boards... > > Is there any particular reason why the dbm690t will not work in virtual > wire mode? > > I think either the sb600 code should call clear_ioapic() instead of > setup_ioapic() or (maybe better) the setup_ioapic() function should get > an additional parameter virtual_wire > > Anyways, maybe we should try to unify clear_ioapic and setup_ioapic > > (also, the function should create a device node and append it to the > bridge it is called from) Sefan, You are right. The sb600 was really doing a clear_ioapic() previously. I don't yet understand why the virtual wire mode causes problems. It is either an additional sb600 setup issue or a mainboard problem with how EXTINT is connected. The setup_ioapic() should probably have more options as EXTINT doesn't have to be connected to the APIC. Signed-off-by: Marc Jones <marcj303@gmail.com> Marc
On 3/5/10 11:02 PM, Marc Jones wrote: > You are right. The sb600 was really doing a clear_ioapic() previously. > I don't yet understand why the virtual wire mode causes problems. It > is either an additional sb600 setup issue or a mainboard problem with > how EXTINT is connected. The setup_ioapic() should probably have more > options as EXTINT doesn't have to be connected to the APIC. > > Signed-off-by: Marc Jones <marcj303@gmail.com> > > Marc > Acked-by: Stefan Reinauer <stepan@coresystems.de>
On Sat, Mar 6, 2010 at 2:35 AM, Stefan Reinauer <stepan@coresystems.de> wrote: > On 3/5/10 11:02 PM, Marc Jones wrote: >> You are right. The sb600 was really doing a clear_ioapic() previously. >> I don't yet understand why the virtual wire mode causes problems. It >> is either an additional sb600 setup issue or a mainboard problem with >> how EXTINT is connected. The setup_ioapic() should probably have more >> options as EXTINT doesn't have to be connected to the APIC. >> >> Signed-off-by: Marc Jones <marcj303@gmail.com> >> >> Marc >> > Acked-by: Stefan Reinauer <stepan@coresystems.de> > r5199 Thanks, Marc
Patch
Index: src/arch/i386/smp/ioapic.c =================================================================== --- src/arch/i386/smp/ioapic.c (revision 5073) +++ src/arch/i386/smp/ioapic.c (working copy) @@ -110,7 +110,7 @@ #endif /* Enable Virtual Wire Mode */ - low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; + low = DISABLED; high = bsp_lapicid << (56 - 32);
If ExtINT is enabled, my board will hang when linux boots. log: ....... Checking if this processor honours the WP bit even in supervisor mode...Ok. SLUB: Genslabs=13, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 Hierarchical RCU implementation. NR_IRQS:512 Console: colour dummy device 80x25 console [ttyS0] enabled spurious APIC interrupt on CPU#0, should never happen. Fast TSC calibration using PIT Detected 2100.411 MHz processor. Calibrating delay loop (skipped), value calculated using timer frequency.. 4200.82 BogoMIPS (lpj=2100411) Mount-cache hash table entries: 512 Initializing cgroup subsys ns Initializing cgroup subsys cpuacct Initializing cgroup subsys freezer CPU: Physical Processor ID: 0 CPU: Processor Core ID: 0 mce: CPU supports 5 MCE banks using C1E aware idle routine Performance Events: AMD PMU driver. ... version: 0 ... bit width: 48 ... generic registers: 4 ... value mask: 0000ffffffffffff ... max period: 00007fffffffffff ... fixed-purpose events: 0 ... event mask: 000000000000000f Checking 'hlt' instruction... end of log. I believe the ExtINT don't have to be enable in BIOS stage. It will be done when the kernel boots. Plus, it is the way my proprietary BIOS does. It is tested on dbm690t. Signed-off-by: Zheng Bao <zheng.bao@amd.com> io_apic_write(ioapic_base, 0x10, low);