| Submitter | Bao, Zheng |
|---|---|
| Date | 2009-08-06 03:00:28 |
| Message ID | <DD1CC71B621B004FA76856E5129D6B1702EFBE3B@sbjgexmb1.amd.com> |
| Download | mbox | patch |
| Permalink | /patch/90/ |
| State | Accepted |
| Headers | show |
Comments
> The code between #if and #endif is only about UMA mode. The > CONFIG_GFXUMA should be 1. > We have another mode called side port mode. It is When the CONFIG_GFXUMA > is 0. > > Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> Thanks, Myles
Thanks, Committed to r4525. -----Original Message----- From: Myles Watson [mailto:mylesgw@gmail.com] Sent: Monday, August 10, 2009 11:33 PM To: Bao, Zheng; 'Coreboot' Subject: RE: [coreboot] [patch] Fix CONFIG_GFXUMA in mtrr.c > The code between #if and #endif is only about UMA mode. The > CONFIG_GFXUMA should be 1. > We have another mode called side port mode. It is When the CONFIG_GFXUMA > is 0. > > Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> Thanks, Myles
Patch
Index: src/cpu/x86/mtrr/mtrr.c =================================================================== --- src/cpu/x86/mtrr/mtrr.c (revision 4505) +++ src/cpu/x86/mtrr/mtrr.c (working copy) @@ -418,7 +418,7 @@ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); -#ifdef CONFIG_GFXUMA +#if (CONFIG_GFXUMA == 1) /* UMA or SP. */ // For now we assume the UMA space is at the end of memory if (var_state.hole_startk || var_state.hole_sizek) {
The code between #if and #endif is only about UMA mode. The CONFIG_GFXUMA should be 1. We have another mode called side port mode. It is When the CONFIG_GFXUMA is 0. Signed-off-by: Zheng Bao <zheng.bao@amd.com> printk_debug("Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");