Comments
Patch
===================================================================
@@ -49,6 +49,24 @@
default n if TINY_BOOTBLOCK
default y
+choice
+ prompt "Bootblock behaviour"
+ default TINY_BOOTBLOCK_NORMAL
+ depends on TINY_BOOTBLOCK
+
+config TINY_BOOTBLOCK_SIMPLE
+ bool "Always load fallback"
+
+config TINY_BOOTBLOCK_NORMAL
+ bool "Switch to normal if CMOS says so"
+
+endchoice
+
+config TINY_BOOTBLOCK_SOURCE
+ string
+ default "tinybootblock_simple.c" if TINY_BOOTBLOCK_SIMPLE
+ default "tinybootblock_normal.c" if TINY_BOOTBLOCK_NORMAL
+
config UPDATE_IMAGE
bool "Update existing coreboot.rom image"
default n
===================================================================
@@ -1,3 +1,4 @@
+#define ASSEMBLY 1
#define __PRE_RAM__
#if CONFIG_LOGICAL_CPUS && \
(defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
@@ -31,17 +32,3 @@
{
asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist));
}
-
-static void main(unsigned long bist)
-{
- if (boot_cpu()) {
- bootblock_northbridge_init();
- bootblock_southbridge_init();
- }
- const char* target1 = "fallback/romstage";
- unsigned long entry;
- entry = findstage(target1);
- if (entry) call(entry, bist);
- asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
-}
-
===================================================================
@@ -1,47 +0,0 @@
-#define __PRE_RAM__
-#if CONFIG_LOGICAL_CPUS && \
- (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
-#include <cpu/x86/lapic/boot_cpu.c>
-#else
-#define boot_cpu(x) 1
-#endif
-
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#else
-static void bootblock_northbridge_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#else
-static void bootblock_southbridge_init(void) { }
-#endif
-
-static unsigned long findstage(char* target)
-{
- unsigned long entry;
- asm volatile (
- "mov $1f, %%esp\n\t"
- "jmp walkcbfs\n\t"
- "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp");
- return entry;
-}
-
-static void call(unsigned long addr, unsigned long bist)
-{
- asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist));
-}
-
-static void main(unsigned long bist)
-{
- if (boot_cpu()) {
- bootblock_northbridge_init();
- bootblock_southbridge_init();
- }
- const char* target1 = "fallback/romstage";
- unsigned long entry;
- entry = findstage(target1);
- if (entry) call(entry, bist);
- asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
-}
-
===================================================================
@@ -1,47 +1,31 @@
-#define __PRE_RAM__
-#if CONFIG_LOGICAL_CPUS && \
- (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
-#include <cpu/x86/lapic/boot_cpu.c>
-#else
-#define boot_cpu(x) 1
-#endif
+#include <tinybootblock_common.h>
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#else
-static void bootblock_northbridge_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#else
-static void bootblock_southbridge_init(void) { }
-#endif
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
-static unsigned long findstage(char* target)
-{
- unsigned long entry;
- asm volatile (
- "mov $1f, %%esp\n\t"
- "jmp walkcbfs\n\t"
- "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp");
- return entry;
-}
-
-static void call(unsigned long addr, unsigned long bist)
-{
- asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist));
-}
-
static void main(unsigned long bist)
{
if (boot_cpu()) {
bootblock_northbridge_init();
bootblock_southbridge_init();
}
- const char* target1 = "fallback/romstage";
+
+ char* image;
+ if (do_normal_boot())
+ image="normal/romstage";
+ else
+ image="fallback/romstage";
+
unsigned long entry;
- entry = findstage(target1);
+ entry = findstage(image);
if (entry) call(entry, bist);
+
+ /* run fallback if normal can't be found */
+ entry = findstage("fallback/romstage");
+ if (entry) call(entry, bist);
+
+ /* duh. we're stuck */
asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
}
===================================================================
@@ -1,37 +1,5 @@
-#define __PRE_RAM__
-#if CONFIG_LOGICAL_CPUS && \
- (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
-#include <cpu/x86/lapic/boot_cpu.c>
-#else
-#define boot_cpu(x) 1
-#endif
+#include <tinybootblock_common.h>
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#else
-static void bootblock_northbridge_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#else
-static void bootblock_southbridge_init(void) { }
-#endif
-
-static unsigned long findstage(char* target)
-{
- unsigned long entry;
- asm volatile (
- "mov $1f, %%esp\n\t"
- "jmp walkcbfs\n\t"
- "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp");
- return entry;
-}
-
-static void call(unsigned long addr, unsigned long bist)
-{
- asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist));
-}
-
static void main(unsigned long bist)
{
if (boot_cpu()) {
===================================================================
@@ -63,7 +63,7 @@
$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.c
$(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@
-$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/i386/init/bootblock.c $(obj)/romcc
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/i386/init/$(subst ",,$(CONFIG_TINY_BOOTBLOCK_SOURCE)) $(obj)/romcc
$(obj)/romcc $(bootblock_romccflags) -O2 $(ROMCCFLAGS) $(INCLUDES) $< -o $@
$(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld
Hi, The attached patch allows the user to select one of multiple tinybootblock handlers. It also adds a new handler that provides fallback/normal behaviour (run normal iff CMOS says so and is present). The handler doesn't work yet (at least in my tests), but should be close. I mostly push this to start a discussion on how we want that part of coreboot to work. The idea would be to install the "normal" handler and fallback images in one pass, and normal images in a later pass using the already commited update feature. More special operations in tinybootblock become possible, too - maybe "run flashrom_romstage if GPIO x is triggered", or "run images X if cpuid is X, images Y if cpuid is Y". To apply the patch, src/arch/i386/init/bootblock.c must be copied to src/arch/i386/include/tinybootblock_common.h src/arch/i386/init/tinybootblock_normal.c src/arch/i386/init/tinybootblock_simple.c and bootblock.c itself be removed (the patch does that, but your patch(1) might not delete the file properly). Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>